対外発表論文一覧

2025年度

論文誌

  1. David Clarino, Naoya Asada, Atsushi Matsuo, Shigeru Yamashita, “Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-based Quantum Circuit Synthesis,” IEICE Transactions on Information and Systems, Vol. E108-D No. 4, pp. 320-329, Apr. 2025.
  2. Yuta Hamachiyo, Chiharu Shiro, Hiroki Nishikawa, Hiroyuki Tomiyama, Shigeru Yamashita, “Target-Guided Droplet Routing on MEDA Biochips Considering Shape-Dependent Velocity Models and Droplet Splitting,” *Biosensors,*MDPI, vol. 15, no. 8, August 2025.
  3. Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, “Simultaneous Routing with Washing Droplets Based on Shape-Dependent Velocity Model in MEDA Biochips,” *Biosensors,*MDPI, vol. 15, no. 8, August 2025.
  4. Koki Suzuki, Shigeru Yamashita, Hiroyuki Tomiyama, Ankur Gupta, “Considering the Node Level in Error Correction for DMFBs, " *Micromachines,*MDPI, vol. 16, no. 9, August 2025.
  5. Zanhe Qi, Atsushi Matsuo, Shigeru Yamashita, “Improving Gaussian Elimination-Based Nearest Neighbor Architecture Circuit Synthesis Method by CNOT Gates Insertion, " IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. J108-D, No. 10, pp. 542-552, Oct., 2025.
  6. Yuta Hamachiyo, Chiharu Shiro, Hiroki Nishikawa, Hiroyuki Tomiyama, Shigeru Yamashita, “Accelerated Droplet Routing on MEDA Biochips Considering Shape-Dependent Velocity Models Through Guidance and Lower-Bound Constraints,” *Applied Sciences,*MDPI, vol. 16, no. 3, February 2026.
  7. Zanhe Qi, Koki Hirono, David Clarino, Shigeru Yamashita, “A Decomposition Method of MCT Gates for Reducing Overall Circuit T-depth, IPSJ Transactions on System LSI Design Methodology, Vol.19, pp. 12-21, Feb. 2026.

国際会議

  1. Shigeru Yamashita, Takashi Horiyama, Norihito Yasuda and Tatsuya Nakao, “Realizing 4-input Functions with the Minimum Toffoli Gate Count,” Proc. 2025 IEEE 55th International Symposium on Multiple-Valued Logic (ISMVL), 2025, pp. 110-116.

  2. Zanhe Qi, Kouki Hirono, David Clarino, Shigeru Yamashita. A Decomposition　Method for MCT Gates Considering T-depth of Each Qubit, Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2025, 1: 1-6.

  3. Yuta Hamachiyo, Chiharu Shiro, Hiroki Nishikawa, Hiroyuki Tomiyama, Shigeru Yamashita, “Fast Droplet Routing on MEDA Biochips Considering Shape-Dependent Velocity Models and Droplet Separation,” International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), Seoul, Korea, July 2025.

  4. Shotaro Karasawa, Chiharu Shiro, Hiroki Nishikawa, Hiroyuki Tomiyama, Shigeru Yamashita, “Accelerating Integer Programming Based Droplet Routing,” International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), Seoul, Korea, July 2025.

  5. Tomohisa Kawakami, Tomoyasu Shimada, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, “Poster: A Comparative Analysis of Machine Learning Models for SAT Runtime Prediction,” International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Singapore, August 2025.

  6. Yuta Hamachiyo, Chiharu Shiro, Hiroki Nishikawa, Hiroyuki Tomiyama, Shigeru Yamashita, “Fast Droplet Routing on MEDA Biochips through Splitting and Target-Guided Constraints,” Taiwan and Japan Conference on Circuits and Systems (TJCAS), Kaohsiung, Taiwan, August 2025.

  7. David Clarino, Chitranshu Arya, Shigeru Yamashita and Zanhe Qi, “A T-count and T-depth optimal 3-input Boolean phase oracle library,” Proc. of AQIS 25, Poster Session 3, pp. 135-137, August 2025.

  8. Taketo Yamaguchi, Shigeru Yamashita and Yosuke Ueno, “Surface code scheduling with consideration for qubit movement Proc. of AQIS 25, Poster Session 3, pp. 172-175, August 2025.

  9. Zanhe Qi, David Clarino and Shigeru Yamashita, “Reducing T-depth in Quantum Oracle Generation by Decomposing MCT Gates,” Proc. of AQIS 25, Poster Session 3, pp. 176-179, August 2025.

  10. Jion Tamamoto, Yuto Matsuda, Daniel Schönberger, Shigeru Yamashita and Robert Wille, “Shuttling for Scalable Trapped-ion Quantum Computers using MAPP,” Proc. of AQIS 25, Poster Session 3, pp. 180-183, August 2025.

  11. Jinrui Zhang and Shigeru Yamashita, “Hybrid Quantum-Classical Feature Learning for Predicting QAOA Solution Quality,” Proc. of AQIS 25, Poster Session 3, pp. 190-192, August 2025.

  12. Yuyao Zhang and Shigeru Yamashita, “Tensor Network Contraction Optimization for Quantum Circuits Based on Time-Step Grouping and Dynamic Programming,” Proc. of AQIS 25, Poster Session 3, pp. 196-199, August 2025.

  13. Kaito Mitsuishi, Yusuke Kimura and Shigeru Yamashita, “Parallelization Methods for Quantum Circuit Simulators Using Quantum Multiple-valued Decision Diagrams,” Proc. of AQIS 25, Poster Session 3, pp. 200-202, August 2025.

  14. Issei Nakamura, Shigeru Yamashita, Hiroyuki Tomiyama, Ankur Guputa, “Speeding Up a Routing Method Considering Droplet Splitting on MEDA Biochips by Dijkstra’s Method,” Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 97 - 102, October 2025.

  15. Purrnima Singh, Yash Gupta, Syed Rameem Zahra, Ankur Gupta, Shigeru Yamashita , “AutoPre-ACM: Autoencoder Based Precision-Enhanced Anomaly Detection For Cyber-Physical Attacks in MEDA Biochips,” Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 20 – 25, October 2025.

  16. Yusuke Igarashi, Shigeru Yamashita, “Extending the Single-Target Droplet Generation Method CoDOS to Multi-Target Synthesis,” Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 154 – 158, October 2025.

  17. Yota Yanagida, Shigeru Yamashita, “Efficient and Accurate SC Arithmetic Circuits Using Bit Manipulation Based on Interval Partitioning of Bit Strings,” Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 211 – 216, October 2025.

  18. Yash Gupta, Purrnima Singh, Syed Rameem Zahra, Ankur Gupta, Shigeru Yamashita, “Error Recovery in MEDA Biochips Using Deep Reinforcement Learning with Electrode Health Awareness,” Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 260 – 265, October 2025.

  19. Nao Shinoda, Zhou Songyu, Shigeru Yamashita, “A Stochastic Number Comparator by Utilizing Positive Correlation,” Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 266 - 271, October 2025.

  20. Issei Nakamura, Shigeru Yamashita, Hiroyuki Tomiyama, Ankur Guputa, “A Polynomial Time Routing Algorithm for MEDA Biochips based on Dijkstra’s Algorithm,” International Conference on VLSI Design (VLSID), Pune, Maharashtra, India, January 2026.

  21. Yuta Hamachiyo, Chiharu Shiro, Hiroki Nishikawa, Hiroyuki Tomiyama, Shigeru Yamashita, “Distance-Guided Routing of Size-2 Droplets with Splitting and Shape-Dependent Velocity on MEDA Biochips,” International Conference on Electronics, Information, and Communication (ICEIC), Macau, January 2026.

  22. Shigeru Yamashita, He Li, Zhiding Liang, Robert Wille, “Design Automation for the Early Fault Tolerant Quantum Computing,” Tutorial in 31st Asia and South Pacific Design Automation Conference (ASP-DAC 2026). (チュートリアル講演）

  23. Shigeru Yamashita, “Exploring the Utilization of Fault-Tolerant Quantum Computers by Using Classical Computers Cooperatively,” QUANTUM SINGAPORE 2026, Feb. 2026. (招待講演）

国内学会

  1. 濱千代裕太, 城千春, 西川広記, 冨山宏之, 山下茂, “目的セルへの誘導制約によるMEDAバイオチップ液滴ルーティングの高速化,” 情報科学技術フォーラム(FIT), 札幌, 2025年9月.

  2. 玉元慈恩, 山下茂, “量子電荷結合デバイスQCCDにおける量子テレポーテーションを組込んだイオンシャトリング” 第53回量子情報技術研究会, 2025-12-QIT-64, 2025年12月2日．

  3. 河上智久, 馬瑞, 嶋田知泰, 孔祥博, 冨山宏之, 山下茂, “充足可能性問題の求解時間を予測する機械学習モデルの評価,” 電子情報通信学会VLD/ICD/HWS研究会, 那覇, 2026年3月.

  4. 長濱丈流, 河上智久, 嶋田知泰, 孔祥博, 冨山宏之, 山下茂,  “ニューラルネットワークによるSATソルバの選択,” 電子情報通信学会VLD/ICD/HWS研究会, 那覇, 2026年3月.

  5. 玉元 慈恩, 山下 茂, “QCCDにおける量子テレポーテーションを用いたイオンシャトリングオーバヘッド削減手法,” 情報処理学会 第203回ハイパフォーマンスコンピューティング・第17回量子ソフトウェア合同研究発表会, 2026年3月.

  6. 戸高 温人, 山下 茂, “探索方法を動的に変更するビームサーチを用いた量子ビットマッピング手法,” 情報処理学会 第203回ハイパフォーマンスコンピューティング・第17回量子ソフトウェア合同研究発表会, 2026年3月.

  7. 三石 海人, 木村 悠介 , 山下 茂, “同時に適用する量子ゲートの適切な選択によるQMDDベースの量子回路シミュレーションの高速化,” 情報処理学会 第203回ハイパフォーマンスコンピューティング・第17回量子ソフトウェア合同研究発表会, 2026年3月.

その他

    1. Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, “Simultaneous Routing with Washing Droplets Based on Shape-dependent Velocity Model,” Workshop on Design Challenges for Microfluidic Chips, Ritsumeikan University, Ibaraki, December 2025.
    2. Shotaro Karasawa, Chiharu Shiro, Hiroki Nishikawa, Hiroyuki Tomiyama, Shigeru Yamashita, “Accelerating Integer Programming Based Droplet Routing on MEDA Biochips,” Workshop on Design Challenges for Microfluidic Chips, Ritsumeikan University, Ibaraki, December 2025.
    3. Yuta Hamachiyo, Chiharu Shiro, Hiroki Nishikawa, Hiroyuki Tomiyama, Shigeru Yamashita, “Distance-Guided Routing of Size-2 Droplets with Splitting and Shape-Dependent Velocity on MEDA Biochips,” Workshop on Design Challenges for Microfluidic Chips, Ritsumeikan University, Ibaraki, December 2025.

2024年度

  1. 山下 茂, “量子計算機と古典計算機の協調利用の枠組みを開発するCRESTの研究プロジェクトの紹介”, 情報処理学会第８７回全国大会, ２０２５年３月１３日　(招待講演）

  2. Shin-ichi Minato, Takeaki Uno, Norihito Yasuda, Takashi Horiyama, Ken-ichi Kawarabayashi, Shigeru Yamashita, Hirotaka Ono, “Algorithmic Foundations for Social Advancement Recent Progress on Theory and Practice,” Springer Nature, March 2025. https://doi.org/10.1007/978-981-96-0668-9

  3. Debraj Kundu, Tsun-Ming Tseng, Shigeru Yamashita and Ulf Schlichtmann, “Effective Sample Preparation Using Loading-Aware Mixing on Programmable Microfluidic Device” to appear in Proc of Design Automation Conference 2025.

  4. Z. Qi, A. Matsuo and S. Yamashita, “Optimization for Gaussian Elimination-Based NNA-Compliant Circuit Synthesis Method by Inserting CNOT Gates,” 2024 IEEE International Conference on Quantum Computing and Engineering (QCE), Montreal, QC, Canada, 2024, pp. 971-978, doi: 10.1109/QCE60285.2024.00116.

  5. D. Clarino, K. Seino, A. Matsuo and S. Yamashita, “Utilizing Don’t-Cares to Minimize CNOTs in Synthesizing NNA Compliant Quantum Circuits,” in 2024 IEEE International Conference on Quantum Computing and Engineering (QCE), Montreal, QC, Canada, 2024, pp. 500-501, doi: 10.1109/QCE60285.2024.10375.

  6. David Clarino, Naoya Asada, Atsushi Matsuo, Shigeru Yamashita, “Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-based Quantum Circuit Synthesis,” IEICE Transactions on Information and Systems, vol. E108-D, no. 4, pp. 320-329, April 2025.

  7. Shigeru Yamashita, Takashi Horiyama, Norihito Yasuda and Tatsuya Nakao, “Realizing 4-input Functions with the Minimum Toffoli Gate Count,” Proc. 2025 IEEE 55th International Symposium on Multiple-Valued Logic (ISMVL), pp. 110-116, 2025.

  8. 鈴木皓貴, 山下茂, 冨山宏之, Ankur Gupta, “DMFBにおけるノードレベルを考慮したノード二重化によるエラー訂正手法,” 電子情報通信学会VLD/HWS/ICD研究会, 沖縄, 2025年3月5日.

  9. 中村一晴, 山下茂, 冨山宏之, Ankur Gupta, “MEDAにおける分割を考慮したルーティング手法のダイクストラ法による高速化,” 電子情報通信学会VLD/HWS/ICD研究会, 沖縄, 2025年3月5日.

  10. 柳田陽太, 山下茂, “区間分割に基づくビット操作を利用した小面積かつ高精度なSC演算回路の検討,” 電子情報通信学会VLD/HWS/ICD研究会, 沖縄, 2025年3月6日.

  11. Debraj Kundu, Tsun-Ming Tseng, Shigeru Yamashita and Ulf Schlichtmann, “Loading-Aware Mixing-Efficient Sample Preparation on Programmable Microfluidic Device,” 2025 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.2025.

  12. David Clarino, Shohei Kuroda, Shigeru Yamashita, “Reducing T-Count in Quantum Circuits Using Alternate Forms of the Relative Phase Toffoli Gate,”  IEICE Transactions on Fundamentals of Electronics, Vol.E108-A, No.2, pp. 1-10, Jan. 2025. 10.1587/TRANSFUN.2023EAP1165  (2024年度電子情報通信学会論文賞 受賞）

  13. 濱千代裕太, 城千春, 西川広記, 冨山宏之, 山下茂, “MEDAバイオチップにおける形依存の速度モデルと分離を考慮した液滴ルーティングの高速化,” 情報処理学会組込みシステム研究会, 横浜, 2024年11月21日.

  14. 柄澤昇太郎, 城千春, 西川広記, 冨山宏之, 山下茂, “整数計画法に基づくMEDAバイオチップ液滴ルーティングの高速化,” 情報処理学会組込みシステム研究会, 横浜, 2024年11月21日.

  15. 山下 茂, “EDA分野の研究者向けの量子回路設計における最適化問題”, 第１回FTQCアーキテクチャ研究会, 2024年11月15日.　(招待講演）

  16. Zanhe QI,  Atsushi Matsuo, Shigeru Yamashita, “Improving Mapping to Nearest Neighbor Architecture by Using Gaussian Elimination-based Method by Changing Qubits’ Order,” Quantum Innovation 2024,  PO-CP-40, Oct. 22, 2024.  (Poster Presentation Awards for Young Researcher 受賞）

  17. David Clarino, Kyouhei Seino, Atsushi Matsuo, Shigeru Yamashita, “Utilizing Don’t-Cares to Minimize CNOTs in Synthesizing NNA Compliant Quantum Circuits”, Quantum Innovation 2024,  PO-CP-23, Oct. 22, 2024.  (Poster Presentation Awards for Young Researcher 受賞）

  18. 中尾龍矢, 山下茂, 堀山貴史, 安田宜仁, “SMTソルバーによるブール関数を実現する量子回路のトフォリゲート数の最小化手法”, 第47回多値論理フォーラム 2024年9月29日.

  19. Shigeru Yamashita, “Quantum Boolean Circuit Design with Relative Phase Toffoli Gates,” Advances in Modern Quantum Science”,  Bukhara, Uzbekistan, Sep. 16, 2024. (招待講演)

  20. Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, “Simultaneous Routing with Washing Droplets in MEDA Biochips,” International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT), pp. 190-201, Kusatsu, Shiga, Japan, August 2024.

  21. 城千春, 西川広記, 孔祥博, 冨山宏之, 山下茂, “MEDAバイオチップにおける形状依存の速度モデルに基づく洗浄を伴う液滴ルーティング,” 情報処理学会DAシンポジウム, pp. 65-71, 2024年8月28日.

  22. David Clarino, Naoya Asada, Atsushi Matsuo and Shigeru Yamashita, “Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-based Quantum Circuit Synthesis,” pp. 424-426, Proc. of AQIS 24 (Aug. 26).

  23. Taketo Yamaguchi and Shigeru Yamashita, “Reducing T Gate Count by Combining Two Types of MCT Gate Decomposition Techniques,” pp. 437-440, Proc. of AQIS 24 (Aug. 26).

  24. Tatsuya Nakao, Shigeru Yamashita and Kyouhei Seino, “NNA Circuit Synthesis Method by SMT Solver Considering Bit Reduction,” pp. 451-453, Proc. of AQIS 24 (Aug. 26).

  25. Zanhe Qi, Atsushi Matsuo and Shigeru Yamashita, “Improving Gaussian Elimination-based Nearest Neighbor Architecture Circuit Synthesis Method with Changing the Order of Qubits,” pp. .378-381, Proc. of AQIS 24 (Aug. 27).

  26. Yuyao Zhang and Shigeru Yamashita, “Using Dynamic Programming and Binary Indexed Tree For Contraction Optimization of Tensor Network Quantum Circuit Simulations,” pp. 382-385, Proc. of AQIS 24 (Aug. 27).

  27. Shunsuke Matsuo, Shigeru Yamashita and Yosuke Ueno, “An Optimization Method for Initial Placement of Logical Qubits in Lattice Surgery using Simulated Annealing,” pp. 389-391, Proc. of AQIS 24 (Aug. 27).

  28. Kensuke Fukui, Shigeru Yamashita, “An Efficient Cost Reduction Method By Reusing Intermediate Droplets in MEDA Biochips,” Proc. of International SoC Design Conference (ISOCC), ET2-1, August 2024.

  29. Suzuki Koki, Shigeru Yamashita, “An Efficient Error Correction Method for DMFBs with Node Redundancy Considering Node Levels,” Proc. of International SoC Design Conference (ISOCC), PS-17, August 2024.

  30. Yuta Hamachiyo, Kaito Mori, Tomohisa Kawakami, Chiharu Shiro, Hiroki Nishikawa, Hiroyuki Tomiyama, Shigeru Yamashita, “Shape-Dependent Velocity Based Droplet Routing Considering Droplet Separation on MEDA Biochips,” International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), Okinawa, Japan, July 2024.

  31. Yuto Arimura, Shigeru Yamashita, “Efficient Realization of an SC Circuit with Feedback and Its Applications,” IEICE Transactions on Fundamentals of Electronics,  Vol.E107-A, No.7, pp. 958-965, July 2024. URL: https://search.ieice.org/offprint/opdl.php?opk=bhkqrstwxz378ABFGJKMNRSTUVWXYZ

  32. Shigeru Yamashita, “Design Methods for Quantum Boolean Circuits,” The Third International Workshop on Quantum Classical Cooperative Computing, June 4, 2024. (招待講演)

  33. Zhidan Zheng, Liaoyuan Cheng, Kanta Arisawa, Qingyu Li, Alexandre Truppel, Shigeru Yamashita, Tsun-Ming Tseng, and Ulf Schlichtmann, “Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip,” In Proc. of the 61st ACM/IEEE Design Automation Conference (DAC ‘24), Article 74, 1–6, June 2024. https://doi.org/10.1145/3649329.3655914

  34. Tomohisa Kawakami, Hiroki Nishikawa, Hiroyuki Tomiyama, Shigeru Yamashita, “DRL-based Voltage Optimization for Multiple Droplet Routing in DMFBs,” Design Automation Conference (DAC), WiP Poster, San Francisco, CA, USA, June 26, 2024.

  35. 廣野航輝, 山下茂, “ビットごとのT-depthを考慮したMCTゲートの分解手法,” 第51回量子情報技術研究会, 2023-05-QIT-51, 2024年5月29日．

  36. 松田悠右人, ダニエルショーンベルガー, 山下茂,　ロバートウィリー, “スケーラブルなイオントラップ量子コンピュータ上でのMulti-Agent経路探 索を利用したイオンシャトリング,” 第51回量子情報技術研究会, 2023-05-QIT-51, 2024年5月29日．

2023年度

  1. Zanhe Qi, Atsushi Matsuo, Shigeru Yamashita, “Optimizing Gaussian Elimination-based NNA-compliant Circuit Synthesis by Simulated Annealing-based CNOT Gates Insertion,” Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 119 - 124, March 2024.
  2. Chuan Lin, Debraj Kundu, Shigeru Yamashita, Hiroyuki Tomiyama, “An Efficient Routing Method for Micro-Electrode-Dot-Array Digital Microfluidic Biochips Considering Droplet Division and Velocity,” Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 287-292, March 2024.
  3. Huan Yu, Atsushi Matsuo, Shigeru Yamashita, “Circuit Division for Gaussian Elimination-based NNA-Compliant Circuit Synthesis Utilizing Reinforcement Learning,” Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 38-43, March 2024.
  4. 山下茂, 堀山貴史, 安田宜仁, “ブール関数を実現する量子回路のトフォリゲート数による列挙の効率化,” 電子情報通信学会技術研究報告, COMP2023-22, Vol. 123, no. 325, pp. 37 - 44, Dec. 2023.
  5. Zanhe QI, “Optimal Mapping to Nearest-Neighbor Architectures by Appling Simulated Annealing-based Gaussian Elimination Iterator,” Quantum Innovation 2023, Nov. 2023.
  6. Huan Yu, “Circuit division based on reinforcement learning to optimize Steiner-Gauss elimination for NNA-compliant quantum circuit synthesis,” Quantum Innovation 2023, Nov. 2023.
  7. David Clarino, “Leveraging different Boolean function decompositions to optimize LUT-based quantum circuit synthesis,” Quantum Innovation 2023, Nov. 2023.
  8. 有村 優斗, 山下 茂, “低面積な補正回路によるSC回路のエラー改善,” 第203回システムとLSIの設計技術研究発表会 (SLDM WIP Forum 2023）ポスター発表, 2023年11月07日.
  9. 清野 恭平, 山下 茂, " ビット削減を考慮したSMTVソルバによるNNA回路合成手法,” 第203回システムとLSIの設計技術研究発表会 (SLDM WIP Forum 2023）ポスター発表, 2023年11月07日.
  10. 平井 将隆, 山下 茂, “混合木の変形による試薬合成におけるフラッシング回数の削減,” 第203回システムとLSIの設計技術研究発表会 (SLDM WIP Forum 2023）ポスター発表, 2023年11月07日.
  11. 松永 卓也, 山下 茂, “辺の集合の分割と配置変更を利用するNNA制約を満たす量子ビット配置の決定手法,” 第203回システムとLSIの設計技術研究発表会 (SLDM WIP Forum 2023）ポスター発表, 2023年11月07日.
  12. 石井 創, 山下 茂, “部分回路間の量子テレポーテーションを利用したNNA回路設計手法,” 第203回システムとLSIの設計技術研究発表会 (SLDM WIP Forum 2023）ポスター発表, 2023年11月07日.
  13. Atsushi Matsuo, Yudai Suzuki, Ikko Hamamura, Shigeru Yamashita, “Enhancing VQE Convergence for Optimization Problems with Problem , " IEICE Transactions on Information and Systems, Vol. E106-D No. 11 pp. 1772-1782, Dec. 2023.
  14. Ryosuke Matsuo, Rudy Raymond, Shin-ichi Minato, Shigeru Yamashita, “Optimizing Decision Diagrams for Measurements of Quantum Circuits, " Proceedings of the 29th Asia and South Pacific Design Automation Conference(ASP-DAC), pp. 134 - 139, Jan. 2024.
  15. D. Clarino, N. Asada and S. Yamashita, “Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean Operations,” 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Francisco, CA, USA, 2023, pp. 1-8, doi: 10.1109/ICCAD57390.2023.10323730.
  16. Kawakami, T.; Shiro, C.; Nishikawa, H.; Kong, X.; Tomiyama, H.; Yamashita, S. A Deep Reinforcement Learning Approach to Droplet Routing for Erroneous Digital Microfluidic Biochips. Sensors 2023, 23, 8924. https://doi.org/10.3390/s23218924 、Nov. 2023
  17. 濱千代 裕太, 森 海翔, 河上 智久, 城 千春, 西川 広記, 冨山 宏之, 山下 茂,  “MEDAバイオチップにおける形依存の速度モデルと分離を考慮した液滴ルーティング,” 情報処理学会第64回組込みシステム研究発表会, 2023年11月16日.
  18. Yuji Wada and Shigeru Yamashita, “Minimizing the Impact of Unbalanced Splitting Errors on DMFBs Without Any Overhead,” Proc. of 26th Euromicro Conference on Digital System Design (DSD), pp531-538, Sep., 2023
  19. Huan Yu, Zanhe Qi and Shigeru Yamashita, “A Comprehensive Strategy for Improving Steiner-Gauss Elimination: Qubit Layout Optimization and Circuit Division,” pp. 17-20, Proc. of AQIS 23.（Best Student Poster Award受賞）
  20. Zanhe Qi, Huan Yu and Shugeru Yamashita. “Optimizing Gaussian Elimination-based NNA-compliant Circuit Synthesis Method by Simulated Annealing-based CNOT Gates Insertion,” pp. 108-110, Proc. of AQIS 23.
  21. Koki Hirono and Shigeru Yamashita, “T-depth Reduction Method by Decomposing MCT Gates Considering the Cancellation,” pp. 231-234, Proc. of AQIS 23.
  22. Kohei Ogino, Atsushi Matsuo and Shigeru Yamashita, “Quantum Circuit Synthesis Method of VQE for Traveling Salesman Problem Considering W States,” pp.  235-238, Proc. of AQIS 23.
  23. David Clarino, Shohei Kuroda and Shigeru Yamashita, “Reducing T-count in Quantum Boolean Circuits by Exploiting Relative Phase Boolean Functions,” pp. 163-165, Proc. of AQIS 23, Aug. 2023
  24. Tomohisa Kawakami, Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, “A Deep Reinforcement Learning-Based Routing Algorithm for Unknown Erroneous Cells in DMFBs,” Interregional NEWCAS Conference, June 2023.
  25. Kaito Mori, Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, “A Fast Approach to Droplet Routing with Shape-Dependent Velocity on MEDA Biochips”, Interregional NEWCAS Conference, June 2023.
  26. 松尾 亮祐, ルディー・レイモンド, 湊 真一, 山下 茂, “量子回路の観測のための決定グラフの最適化.” 第9回量子ソフトウェア研究発表会 2023年6月30日
  27. 中尾龍矢, レイモンド ルディー, 山下茂, “QRACを用いたQAOAの使用量子ビット数の削減手法,” 第48回量子情報技術研究会, 2023-05-QIT-48, 2023年5月29日．
  28. 荻野浩平, 松尾惇士, 山下茂, “W状態を考慮した巡回セールスマン問題向けのVQEの量子回路合成手法.” 第48回量子情報技術研究会, 2023-05-QIT-50, 2023年5月29日．
  29. Zanhe Qi, 山下茂, “ガウス消去法を繰り返し利用するNNA量子回路の最適化手法,” 第48回量子情報技術研究会, 2023-05-QIT-51, 2023年5月29日．
  30. *David Clarino, Shohei Kuroda, and Shigeru Yamashita, “*Using S Gates and Relative Phase Toffoli Gates to Improve T-Count in Quantum Boolean Circuits,” Proc. of IEEE International Symposium on Multiple-Valued Logic, pp. 147-152, May 2023
  31. Zanhe QI, Huan YU and Shigeru Yamashita, “Improving Gaussian Elimination-based NNA-compliant Circuit Synthesis Method by Inserting CNOT Gates,” 32nd International Workshop on Post-Binary ULSI Systems, May 2023.
  32. Huan Yu, Zanhe Qi, Shigeru Yamashita, “Improving Steiner-Gauss Elimination by Utilizing Optimized Qubit Layouts,” 32nd International Workshop on Post-Binary ULSI Systems, May 2023.
  33. Huan Yu, Zhengton Han, Zanhe Qi and Shigeru Yamashita, “Circuit Division based on the Orientation of CNOT Gates for NNA Compliant Circuit Synthesis by Steiner Gauss Elimination,” Reed-Muller 2023, May 2023.

2022年度

  1. 山下茂, “量子技術の実用化と研究開発業務への導入”, 分担執筆：第4章第3節担当, 2023年1月31日発刊, 技術情報協会.
  2. 山下 茂, 高校生に量子暗号の原理を体得してもらう方法, 電子情報通信学会　通信ソサイエティマガジン, 2022, 16 巻, 1 号, p. 38-45, 2022/06/01 https://doi.org/10.1587/bplus.16.38
  3. Kyohei Seino, Shigeru Yamashita, “An SMT-Solver-Based Synthesis of NNA-Compliant Quantum Circuits Consisting of CNOT, H and T Gates.,” 28th Asia and South Pacific Design Automation Conference (ASP-DAC2023), pp. 196-201, 2023.
  4. D. Kundu, V. L. Sarvasiddi, S. Bhattacharjee, S. Yamashita and S. Roy, “Preparing Fluid Samples under Retention Time Constraints using Flow-based Microfluidic Biochips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 9, pp. 3021-3030, Sept. 2023, doi: 10.1109/TCAD.2023.3237980.
  5. Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita, “An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement,”  IEICE Transactions on Fundamentals of Electronics,  Vol.E106-A, No.2, pp. 124-132, Feb. 2023.  https://doi.org/10.1587/transfun.2022EAP1050
  6. Shohei Kuroda and Shigeru Yamashita, “Optimization of Quantum Boolean Circuits by Relative-Phase Toffoli Gates,”  Proc. of Reversible Computation 2022, pp. 20–27, Jul. 2022. https://doi.org/10.1007/978-3-031-09005-9_2
  7. Ikuru Yoshida, Shigeru Yamashita, " Making General Dilution Graphs Robust to Unbalanced-Split Errors on Digital Microfluidic Biochips,”  Vol. E106.A, No. 2, pp. 97-105, Feb. 2023. https://doi.org/10.1587/transfun.2021EAP1174
  8. Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, Sudip Roy, “Shape-Dependent Velocity based Droplet Routing on MEDA Biochips,” IEEE Access, vol. 10, pp. 122423-122430, November 2022.
  9. Masataka Hirai, Debraj Kundu, Shigeru Yamashita, Sudip Roy, Hiroyuki Tomiyama, “Transport-Free Placement of Mixers for Realizing Bioprotocol on Programmable Microfluidic Devices,” International Conference on VLSI Design, Hyderabad, India, January 2023.
  10. Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, “Multi-Droplet Routing Based on a Shape-Dependent Velocity Model on MEDA Biochips,” In Proc. of International Conference on Electronics, Information, and Communication (ICEIC), pp. 178-181, Singapore, February 2023.
  11. Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, “Minimization of MEDA Biochip-Size in Droplet Routing,” Biosensors, MDPI, vol. 12, no. 5, article 277, May 2022. https://doi.org/10.3390/bios12050277
  12. Syoki Kawaminami , Yukino Watanabe and Shigeru Yamashita, “Approximating stochastic numbers to reduce latency” it - Information Technology, vol. 64, no. 3, 2022, pp. 109-118.  https://doi.org/10.1515/itit-2021-0041
  13. Ghosh, D. Kundu, S. Poddar, S. Yamashita, R. Wille, and S. Roy, “Microfluidic Dilution by Recycling Arbitrary Stock Solutions using Various Mixing Models,” In International Symposium on Devices, Circuits and Systems (ISDCS), 2022.
  14. Yifang Bao, Shigeru Yamashita, Bing Li, Tsung-Yi Ho, “Mixer-Based Washing Methods for Programmable Microfluidic Devices,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E105-A, No.10, pp.1385-1391. DOI: 10.1587/transfun.2021EAP1114
  15. Masataka Hirai, Shigeru Yamashita, Sudip Roy, Hiroyuki Tomiyama, “Binding and Scheduling of 2×3 Mixers for Transport-Free Sample Preparation Using Programmable Microfluidic Devices,” In Proc. of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 32-37, Hirosaki, Oct. 2022.
  16. Kyohei Seino, Shigeru Yamashita, “Optimal Synthesis of NNA-Compliant Quantum Circuits in 2-D Architectures by Utilizing Don’t Care Conditions,” In Proc. of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp.  109 - 114, Hirosaki, Oct. 2022. （Outstanding Paper Award受賞）
  17. Yuto Arimura, Shigeru Yamashita, “An Efficient Realization of Power-Root SC Calculations by Inserting Bits,” In Proc. of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 184 - 189, Hirosaki, Oct. 2022.
  18. Sudip Roy, Shigeru Yamashita and Debraj Kundu, “Optimization Problems for Design Automation of Microfluidic Biochips: Scope of Machine Learning,” Tutorial in 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023).
  19. 城千春, 森海翔, 西川広記, 孔祥博, 冨山宏之, 山下茂, “MEDAバイオチップにおける形依存の速度モデルを利用した液滴輸送最短問題, 組込みシステム技術に関するサマーワークショップ, インタクティブセッション, 下呂, 2022年9月.
  20. 城千春, 西川広記, 孔祥博, 冨山宏之, 山下茂, “MEDAバイオチップにおける形依存の速度モデルを利用した液滴ルーティング問題,”” 情報処理学会組込みシステム研究会, 横浜, 2022年11月.
  21. 森海翔, 城千春, 西川広記, 孔祥博, 冨山宏之, 山下茂, “MEDAバイオチップのルーティング問題における最適な液滴操作決定手法,” 情報処理学会組込みシステム研究会, 横浜, 2022年11月.
  22. 城千春, 西川広記, 孔祥博, 冨山宏之, 山下茂, “MEDAバイオチップにおける形依存の速度モデルを利用した複数液滴ルーティング問題,” 電子情報通信学会VLD/RECONF/情報処理学会SLDM研究会, 横浜, 2023年1月. （情報処理学会 第201回SLDM研究発表会 優秀発表賞受賞）
  23. Atsushi Matsuo, Shigeru Yamashita, Daniel J. Egger, “A SAT approach to the initial mapping problem in SWAP gate insertion for commuting gates,” 第8回量子ソフトウェア研究発表会, 2023年3月.
  24. 河上智久, 城千春, 西川広記, 孔祥博, 冨山宏之, 山下茂, “DMFBにおける未知のエラーを考慮した深層強化学習を用いた経路最適化,” 電子情報通信学会VLD/HWS研究会, 沖縄, 2023年3月.
  25. 城千春, 西川広記, 孔祥博, 冨山宏之, 山下茂, “MEDAバイオチップにおける洗浄を伴うルーティング,” 電子情報通信学会VLD/HWS研究会, 沖縄, 2023年3月.
  26. 清野恭平, 山下茂, “SMTソルバを用いたNNA制約を満たす量子回路の合成手法,”  電子情報通信学会VLD/HWS研究会, 沖縄, 2023年3月. （IEICE VLD Excellent Student Author Award 受賞記念講演）
  27. Zanhe Qi, Shigeru Yamashita, “Mapping to Nearest-Neighbor Architectures by Applying Gaussian Elimination Iteratively,” 第47回量子情報技術研究会, 2022-12-QIT-47, 2022年12月8日．
  28. Yu Huan, Shigeru Yamashita, “Determining Initial Qubit Layouts for Steiner-Gauss Elimination,” 第47回量子情報技術研究会, 2022-12-QIT-50, 2022年12月8日．
  29. David Lawrence Bantug Clarino, Shohei Kuroda, Shigeru Yamashita, “Using S Gates and Relative Phase Toffoli Gates to Improve T-Count depth in Quantum Boolean Circuit,” 第47回量子情報技術研究会, 2022-12-QIT-53, 2022年12月8日.
  30. Kundu, V. L. Sarvasiddi, S. Bhattacharjee, S. Yamashita and S. Roy, “Preparing Fluid Samples under Retention Time Constraints using Flow-based Microfluidic Biochips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2023.3237980.
  31. David Clarino, Shohei Kuroda, Shigeru Yamashita, “Using S Gates and Relative Phase Toffoli Gates to Improve T-Count in Quantum Boolean Circuits,” AQIS 2022, Dec. 2022.
  32. Zanhe Qi and Shigeru Yamashita, “Mapping to Nearest-Neighbor Architectures by Appling Gaussian Elimination Iteratively,” AQIS 2022, Dec. 2022.
  33. Yu Huan, Shigeru Yamashita, “Improving Steiner-Gauss Elimination by Changing Initial Qubit Layouts,” AQIS 2022, Dec. 2022.
  34. Atsushi Matsuo, Shigeru Yamashita, Daniel J. Egger, “A SAT approach to the initial mapping problem in SWAP gate insertion for commuting gates,” AQIS 2022, Dec. 2022.

2021年度

  1. Atsushi Matsuo, Shigeru Yamashita, Daniel J. Egger, “A SAT approach to the initial mapping problem in SWAP gate insertion for commuting gates,” IEICE Transactions on Fundamentals of Electronics, Vol.E106-D, No.11, pp.1772-1782, Dec. 2021.
  2. 山下 茂,“量子回路設計における最適化問題,” 電子情報通信学会Fundamentals Review 2021 年 14 巻 4 号 p. 337-346，2021年4月1日発行. （招待論文）
  3. Shuaijie Ying, Sudip Roy, Juinn-Dar Huang and Shigeru Yamashita, “Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip,” Proc. 24th Euromicro Conference on Digital System Design (DSD), pp. 484-494.
  4. Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, “Minimization of Routing Area in MEDA Biochips,” In Proc. of Biomedical Circuits and Systems Conference (BioCAS), Online, October 2021.
  5. 川南翔貴, 山下茂, “3線式SNを用いた演算手法,” デザインガイア2021,信学技報, vol. 121, no. 277, VLD2021-26, pp. 54-59, 2021年12月.
  6. 市川克泰, 山下茂, “Stochastic Computingにおける加算の演算精度の向上手法,” デザインガイア2021, 信学技報, vol. 121, no. 277, VLD2021-27, pp. 60-65, 2021年12月.
  7. 和田有史, 山下茂, “Digital Microfluidic Biochipにおけるエラー同士の相殺を利用したエラー訂正手法,” デザインガイア2021, 信学技報, vol. 121, no. 277, VLD2021-28, pp. 66-71, 2021年12月.
  8. 石田滉, 山下茂, “拡張ネットワークフローモデルの最適な階層数を求める手法,” デザインガイア2021, 信学技報, vol. 121, no. 277, VLD2021-29, pp. 72-77, 2021年12月.
  9. 浅田尚也, 山下茂, “位相がずれたToffoliゲートの厳密最小化手法,” 第45回量子情報技術研究会, 2021-11-QIT, 2021年11月30日．
  10. チョウ キ, 山下茂, “Stochastic Computing における相関を利用した演算を連続して行うための相関を制御する手法の検討,” 信学技報, vol. 121, no. 342, VLD2021-49, pp. 1-6, 2022年1月.
  11. Shoki Kawaminami, Shigeru Yamashita, “Triple-Rail Stochastic Number and Its Applications,” Proc. ISOCC 2021, pp. 161-162, 2021.
  12. 城千春, 西川広記, 孔祥博, 冨山宏之, 山下茂, “MEDAバイオチップにおける使用面積の最小化,” 回路とシステムワークショップ論文集, オンライン, pp. 219-224, 2021年8月.
  13. Terumi Oguri and Shigeru Yamashita，”T-depth Reduction Considering Multiple MCT Gates with Ancilla Bits,” Bookelet of AQIS 2021 Poster Session, pp. 40-42, Sep. 2021.
  14. Duo Xu and Shigeru Yamashita，”Quantum State Preparation By Gaussian Elimination," Bookelet of AQIS 2021 Poster Session, pp. 143-146, Sep. 2021.
  15. Shohei Kuroda and Shigeru Yamashita，”A Cost Reduction Method for Quantum Boolean Circuits by Applying The Transduction Method," Bookelet of AQIS 2021 Poster Session, pp. 220-222, Sep. 2021.
  16. Naoya Asada and Shigeru Yamashita, “Exact Minimization of a Relative-Phase Toffoli Gate, "  25th Annual Conference on Quantum Information Processing, March 2022.

2020年度

  1. Shuaijie Ying, Shigeru Yamashita, “Efficient Sample Preparation for Programmable Microfluidic Devices with Defect Valves,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), R1-5, March 2021.
  2. Katsuhiro Ichikawa, Shigeru Yamashita, “Evaluation of Multiply Accumulators with Stochastic Numbers for Image Processing,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), R1-8, March 2021.
  3. **［IEEE CEDA All Japan Joint Chapter SASIMI Young Researcher Award 2021受賞］**Kanta Arisawa, Shigeru Yamashita, Tsun-Ming Tseng, “MRR Usage Optimization for WRONoC Topology Generation and Communication Parallelism Depending on Bandwidth Requirements,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), R2-2, March 2021.
  4. Ryuya Sakamoto, Shigeru Yamashita, “A Fast Mixing Method of Multiple Reagents on Programmable Microfluidic Devices,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), R2-9, March 2021.
  5. Ikuru Yoshida, Shigeru Yamashita, “Transformation of Mixing Graphs Considering Splitting Errors on Digital Microfluidic Biochip,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), R4-10, March 2021.
  6. **［VLD Excellent Student Award 受賞記念講演］**Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita, “Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures,” VLD2020-73, VLSI設計技術研究会, 2021年3月3日
  7. Debraj Kundu, Jitendra Giri, Sataru Maruyama, Sudip Roy, Shigeru Yamashita, “Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution,” Integration, Volume 78, pp. 95-109, 2021.
  8. Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita, “Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures,” 26th Asia and South Pacific Design Automation Conference (ASP-DAC2021), pp. 786–791, 2021.
  9. Katsuhiro Ichikawa, Shigeru Yamashita, “A Multiply Accumulator for Stochastic Numbers Without Scaling Errors,” To apper in Proc. of  34th International Conference on VLSI Design and 20th International Conference on Embedded Systems (VLSID), 2021.［2020年度 情報理工学研究科研究奨励賞受賞］
  10. Atsushi Matsuo, Yudai Suzuki, Shigeru Yamashita，“Problem-specific Parameterized Quantum Circuits of the VQE Algorithm for Optimization Problems, in Proc. of AQIS 2020, p. 51, Dec. 2020.
  11. HAN Zhengtong, Shigeru Yamashita, “Quantum Circuit Design by Steiner-Gauss with Considering the Order of Qubits,” in Proc. of AQIS 2020, p. 188, Dec. 2020.
  12. Risa Segawa, Shigeru Yamashita, “An Efficient Generation of Arbitrary Superposition of Basis States,” in Proc. of AQIS 2020, p. 211, Dec. 2020.
  13. Atsushi Matsuo, Yudai Suzuki, Shigeru Yamashita, “Problem-specific Parameterized Quantum Circuits of the VQE Algorithm for Optimization Problems”, 情報処理学会第1回量子ソフトウェア研究発表会, 研究報告量子ソフトウェア, 2020-QS-1, 17, pp. 1-9, 2020．
  14. HAN ZHENGTONG，山下茂，”量子ビットの処理順序を考慮したシュタイナーガウス消去法による量子回路の設計,”　デザインガイア2020, 信学技報, vol. 120, no. 234, VLD2020-23, pp. 72-77, 2020年11月.
  15. Ou Suiketsu, Yamashita Shigeru, Sudip Roy, Juinn-Dar Huang, “Restricted-Area and Fast Sample Preparation of a Fluid using Programmable Microfluidic Devices,” デザインガイア2020, 信学技報, vol. 120, no. 234, VLD2020-25, pp. 84-89, 2020年11月.
  16. 吉田育流, 山下茂, “DMFBにおいて分割誤差を考慮した混合グラフの変形,” デザインガイア2020, 信学技報, vol. 120, no. 234, VLD2020-26, pp. 90-94, 2020年11月.
  17. 市川克泰，山下茂, “加算による演算誤差を抑えたStochastic Computing積和演算器,” 2020年電子情報通信学会ソサイエティ大会, AS-1-1, オンライン開催, 2020年9月.
  18. 有澤寛太，山下茂，Tsun-Ming Tseng，”複数の共振モードを考慮した光 NoC におけるトポロジー生成手法,” 2020年電子情報通信学会ソサイエティ大会, C-3/4-6, オンライン開催, 2020年9月.
  19. Gautam Choudhary, Sandeep Pal, Debraj Kundu, Sukanta Bhattacharjee, Shigeru Yamashita, Bing Li, Ulf Schlichtmann and Sudip Roy, “Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays,” 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1335-1338, 2020.
  20. S. Maruyama, D. Kundu, S. Yamashita and S. Roy, “Optimization of Fluid Loading on Programmable Microfluidic Devices for Bio-protocol Execution,” 25th Asia and South Pacific Design Automation Conference (ASP-DAC2020 ), pp. 550-555, 2020.
  21. 山下 茂,「量子回路の設計手法に関する研究動向」,情報処理学会連続セミナー2020 　量子コンピュータとソフトウェア，2020年12月14日.
  22. 山下茂, “量子回路設計,” 情報処理学会 量子ソフトウェア研究会月例バーチャルセミナー, 2020年8月25日
  23. 山下茂，”量子ソフトウエア研究会の紹介とSLDM研究会との連携の期待," 招待講演，情報処理学会　DAシンポジウム 2020, 2020年9月9日

2019年度

  1. Jingwen Ding and Shigeru Yamashita, “Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2D architecture and its Application to Large-scale Circuits,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, PP. 1-1, 27 March 2019.
  2. Kota Asahi, Shigeru Yamashita, Compaction of Topological Quantum Circuits by Modularization, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E102-A, No.4, pp.624-632, Apr. 2019.
  3. 梅田悠人  山下茂 , 整数計画ソルバーを用いたNetworked Labs-on-Chipの設計手法, 電子情報通信学会論文誌 D, Vol.J102-D, No.6, pp.423-433, 2019年6月.
  4. 浅井孝太, 星孝太郎, 山下茂, 大規模TQEC回路の自動最適化手法, 電子情報通信学会論文誌 D，Vol.J102-D,　No.05,　pp.367-377,　2019年5月.
  5. C. Liu, C. Lin, Y. Chen, C. Wu, C. Wang and S. Yamashita, “Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 12, pp. 2284-2297, Dec. 2019. (Best Paper Candidate!)
  6. Wakaki Hattori and Shigeru Yamashita, “Mapping to 2D Nearest Neighbor Architecture by Changing the Gate Order,”  IEICE Transactions on Information and Systems,  Vol.E102-D, No.11, pp.2127-2134，Nov. 2019.
  7. Yudai Sakamoto and Shigeru Yamashita, “Efficient Methods to Generate Constant SNs with Considering Trade-off between Error and Overhead and Its Evaluation,” IEICE Transactions on Information and Systems, Vol.E103-D, No.02, pp. 321-328, Feb. 2020.
  8. 山下茂 (招待講演), EDA分野におけるラボオンチップの最適設計に関する研究, DAシンポジウム 2019, 2019年 　8月28日
  9. 山下茂 (招待講演),  量子回路設計、情報科学技術フォーラム（FIT）イベント企画：量子コンピュータ技術基盤の創出に向けて、20192019年9月4日
  10. 山下茂 (招待講演), 量子回路設計における最適化問題,  VLD研究会, 2019年11月15日
  11. Wakaki Hattori and Shigeru Yamashita, The decomposition of an MPMCT gate in consideration of NNA, in Proc. of AQIS 2019, pp. 134-135,  Aug. 2019.
  12. Kota Asai and Shigeru Yamashita Efficient Mapping of the ZX calculus, in Proc. of AQIS 2019, pp. 139-141,  Aug. 2019.
  13. Risa Segawa, Shigeru Yamashita, and Rudy Raymond, Minimizing Quantum Circuits for Simultaneous Two-Qubit Measurement by Single-Qubit Measurements, in Proc. of AQIS 2019, pp. 176-177,  Aug. 2019.
  14. Yohei Wakabayashi and Shigeru Yamashita, A handy condition of bridge compression for topological quantum circuits, in Proc. of AQIS 2019, pp. 180-181,  Aug. 2019.
  15. Maximum Error-Aware Design of Approximate Array Multipliers, Kenta Shirane, Takahiro Yamamoto, Ittetsu Taniguchi, Yuko Hara-Azumi, Shigeru Yamashita, Hiroyuki Tomiyama，Prod. of International SoC Design Conference (ISOCC),  pp73-74, 2019 Oct.
  16. Yukino Watanabe, Shigeru Yamashita,  “A New Approach to Express Stochastic Numbers,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 95-98 (R2-3), Oct 2019.
  17. Ikuru Yoshida, Kota Asai, Tsung-Yi Ho, Shigeru Yamashita, “Droplet Splitting Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 110 - 115 (R2-6), Oct 2019.
  18. Ying Shuaijie, Sudip Roy, Juinn-Dar Huang, Shigeru Yamashita, “Sample Preparation with Efficient Dilution of Biochemical Fluids using Programmable Microfluidic Devices,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI),  pp. 122 - 125 (R2-9), Oct 2019.
  19. Yuto Umeda, Sudip Roy, Shigeru Yamashita, “Mixing of Biochemical Fluids using Programmable Microfluidic Devices,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 144 - 149 (R2-14), Oct 2019.
  20. Kazuki Morita, Wakaki Hattori, Shigeru Yamashita, “A Layout Design Method of QCA without Fixing Data Flow,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 256 - 261 (R4-2), Oct 2019.
  21. Bao Yifang, Bing Li, Tsung-Yi Ho, Shigeru Yamashita, “Performance Improvements for Block-Flushing,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 268 - 269 (R4-4), Oct 2019.
  22. Yudai Sakamoto, Shigeru Yamashita, “Effect of Reducing the Bit Length of LFSRs for SC,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 280 - 285 (R4-7), Oct 2019.
  23. Matsuo A., Yamashita S., An Efficient Method for Quantum Circuit Placement Problem on a 2-D Grid, pp. 162-168 In: Thomsen M., Soeken M. (eds) Reversible Computation. RC 2019. Lecture Notes in Computer Science, vol 11497, 2019.

2018年度

  1. 山下茂，「量子コンピュータ／イジング型コンピュータ研究開発最前線」第1章，第２節：量子回路設計手法，情報機構，2019年2月
  2. Gupta, Ankur, Huang, Juinn-Dar,Yamashita, Shigeru, Roy, Sudip, Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device–Based Biochips, ACM Transactions on Design Automation of Electronic Systems. Vol. 24, No. 2, pp. 1–24. Feb. 2019
  3. Co Kang-Yi Fan, Shigeru Yamashita  and Juinn-Dar Huang,  Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips using Network Flow Models, Proc. of International Symposium on VLSI Design, Automation & Test (VLSI-DAT), D6-1, Apr. 2019**（Best Paper Candidate)**
  4. Yudai Sakamoto, Shigeru Yamashita, Reducing the Overhead of Stochastic Number Generators Without Increasing Error, in the Proceedings of 32th International Conference on VLSI Design, pp. 52-57, Jan. 2019
  5. 梅田悠人, 山下茂, NLoCの自動設計手法と最適な構造の提案, 信学技報, VLD2018-40, 2018年11月
  6. 坂本雄大, 山下茂, 演算誤差と回路面積のトレードオフを考慮したStochastic Numberの生成手法, 信学技報, VLD2018-47, 2018年11月
  7. 渡邊 結希乃、⼭下 茂, Approximate Computingを利⽤した配列型乗算器の遅延故障への対処法,  2018 年度情報処理学会関西支部支部大会,  A-01, 2018年9月
  8. 坂本 雄⼤、⼭下 茂, SCの定数⽣成におけるエラー率を考慮した⾯積コスト削減⼿法,  2018 年度情報処理学会関西支部支部大会,  A-02, 2018年9月
  9. 梅⽥ 悠⼈、⼭下 茂, 整数計画ソルバーを⽤いたNetworked Labs-on-Chipの設計 ⼿法,  2018 年度情報処理学会関西支部支部大会,  A-03, 2018年9月 (推薦論文に選出されました!）
  10. Takahiro Yamamoto, Kenta Shirane, Ittetsu Taniguchi, Hiroyuki, Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi, A Systematic Approach to Design of Approximate Array Multipliers, Taiwan and Japan Conference on Circuits and Systems (TJCAS), Aug. 2018. (Student Presentation Award受賞)
  11. Wakaki Hattori and Shigeru Yamashita,  Mapping to 2D Nearest Neighbor Architecture by a SAT solver and A* algorithm, in Proc. of AQIS 2018, p. 72, Sep., 2018.
  12. Kota Asai and Shigeru Yamashita, Compaction of Topological Quantum Circuits by Modularization, in Proc. of AQIS 2018, p. 73, Sep., 2018.
  13. Jingwen Ding and Shigeru Yamashita, Exact and Approximate Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D architectures, in Proc. of AQIS 2018, p. 91, Sep., 2018.
  14. Wakaki Hattori, Shigeru Yamashita, Quantum Circuit Optimization by Changing the Gate Order for 2D Nearest Neighbor Architectures, Lecture Notes in Computer Science Volume 11106, 2018, pp. 228-243 (Reversible computation 2018, Sep. 2018.)
  15. 山下茂，松尾惇士, 量子回路設計と最適化，オペレーションズ・リサーチ**,** Vol.63　No.6**, pp.  342- 349,** 2018年6月．

2017年度

  1. Nurul Ain Binti Adnan, Shigeru Yamashita, Logical Qubit Layout Problem for ICM Representation, Journal of Information Processing, Volume 26 (2018) Pages 20-28, January 15, 2018.
  2. Placement of Reagents on Programmable Microfluidic Device, Satoru Maruyama, Ankur Gupta, Sudip Roy, Shigeru Yamashita, Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), R2-1, March 2018. (Outstanding Paper Award)
  3. On Optimization Methods for Decision Diagrams to Represent Probabilities, Kodai Abe, Kentaro Haneda, Shigeru Yamashita,  Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), R2-3, March 2018.
  4. 山下茂、「電子情報通信学会 100年史」D 情報・システム 第1章 コンピュータシステム,  1.2 計算理論，並列・分散計算処理の節, 電子情報通信学会, 2017
  5. Graph-Covering-Based Architectural Synthesis for Programmable Digital Microfluidic Biochips, Daiki Kitagawa, Dieu Quang Nguyen, Trung Anh Dinh. Shigeru Yamashita, International Journal of Biomedical and Clinical Engineering (IJBCE), Article 3, Volume 6: 2 Issues (2017)
  6. Stochastic Number Generation with the Minimum Inputs. Ritsuko Muguruma, Shigeru Yamashita, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E100.A (2017) No. 8 pp. 1661-1671.
  7. Reduction of Quantum Cost by Making Temporary Changes to the Function, Nurul Ain Binti Adnan, Shigeru Yamashita, Alan Mischenko, IEICE Transactions on Information and Systems, Vol. E100.D (2017) No. 7 pp. 1393-1402
  8. A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers, Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, Volume E100-A No.7, pp.1496-1499.
  9. 山元 貴普, 谷口 一徹, 冨山 宏之, 山下 茂, 原 祐子,  “改良型配列型近似乗算器の設計と解析,” 回路とシステムワークショップ, 2017年5月.
  10. Systematic Design of Approximate Array Multipliers with Different Accuracy, Takahiro Yamamoto, Hiroyuki Tomiyama, Ittetsu Taniguchi, Shigeru Yamashita, and Yuko ara-Azumi, In International Workshop on Highly Efficient Neural Networks Design, 2017
  11. An Ancilla Reduction Technique for Quantum Circuits Converted from NAND-based Circuits, Soma Esaki, Masato Onoda and Shigeru Yamashita, in Proc. of AQIS 2017, pp. 289-290, Sep. 2017
  12. Synthesis of Physical-Limitation-Aware Optimal Quantum Circuits in 2-D Architecture, Jingwen Ding and Shigeru Yamashia, in Proc. of AQIS 2017, pp. 298-299, Sep. 2017.
  13. Quantum Circuit Design by Using ESOP Minimization,  Masato Onoda and Shigeru Yamashita, in Proc. of AQIS 2017, pp. 423-424, Sep. 2017.
  14. Locating Loops for TCSC Considering Bridge Transformation, Kentaro Haneda and Shigeru Yamashita, in Proc. of AQIS 2017, pp .425-426, Sep. 2017

2016年度

  1. Ambainis, K. Iwama, M. Nakanishi, H. Nishimura, R. Raymond, S. Tani, S. Yamashita, “Quantum Query Complexity of Almost All Functions with Fixed On-Set Size," Computational Complexity,Volume 25, Issue 4, pp 723–735, December 2016, Springer International Publishing.
  2. Masato Onoda, Kouhei Kushida and Shigeru Yamashita, “*Optimization of Quantum Circuits with Multiple Outputs,"*in Proc. of AQIS 2016, pp. 188-189, Aug. 2016.
  3. Kotaro Hoshi and Shigeru Yamashita, “*Parallelization of Braiding Operations for Topological Quantum Computation,"*in Proc. of AQIS 2016, pp. 190 -191, Aug. 2016.
  4. Kentaro Haneda, Shigeru Yamashita, Simon Devitt and Kae Nemoto “*Reducing Loops for Topological Cluster State Quantum Computation,"*in Proc. of AQIS 2016, pp.208 -209, Aug. 2016.
  5. Nurul Ain Binti Adnan, Kouhei Kushida and Shigeru Yamashita *Reduction of Quantum Cost by Changing the Functionality,*in Proc. of AQIS 2016, pp. 212-213, Aug. 2016.
  6. Ain Binti Adnan, Kouhei Kushida and Shigeru Yamashita，“A Pre-Optimization Technique to Generate Initial Reversible Circuits with Low Quantum Cost,”  Proc. of 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2298-3001, May 2016.
  7. Kodai Abe, Shigeru Yamshita, “A Decision Diagram to Analyze Probabilistic Behavior of Circuits, " Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), R2-6, Oct. 2016.
  8. Balasubramanian and S. Yamashita, “Area/Latency Optimized Early Output Asynchronous Full Adders and RelativeTimed Ripple Carry Adders,” SpringerPlus, 5(1), 1-26, 2016.
  9. Yamamoto, I. Taniguchi, H. Tomiyama, S. Yamashita and Y. Hara-Azumi, “A systematic methodology for design and analysis of approximate array multipliers,” 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, 2016, pp. 352-354.
  10. 渡邉 朗弘，山下 茂, “Stochastic Computingにおける相関の許容によるSNGの削減,”  ETNET2017 (19),  2017年3月9日.
  11. 壷阪 幸輝，山下 茂, “Stochastic Computingにおけるマルチプレクサの制御入力として複雑な式を用いる回路設計,” ETNET2017 (20) 2017年3月9日.
  12. 北川 大樹，山下 茂, “試料生成における汚染問題を考慮したDMFB合成手法,” ETNET2017 (21) 2017年3月9日.
  13. 六車利都子, 山下茂,  “最小の入力数でStochastic Numberを生成する回路設計手法, " 電子情報通信学会技術研究報告 116(330), 1-6, 2016-11-28.
  14. ⼩野⽥ 将⼈、⼭下 茂、櫛⽥ 耕平, “複数出⼒を考慮した量⼦回路設計⼿法,”  2016年度情報処理学会関西支部支部大会,  G-20, 2016年9月26日. 学生優秀発表賞
  15. ⽻⽥ 健太郎、⼭下 茂、Simon Devitt、根本 ⾹絵, “クラスタ状態TQC回路のループ削減⼿法,” 2016 年度情報処理学会関西支部　支部大会,  G-20, 2016年9月26日. 支部大会奨励賞受賞
  16. 山元 貴普, 谷口 一徹, 冨山 宏之, 山下 茂, 原 祐子, “配列型近似乗算器の設計と解析,” 回路とシステムワークショップ, pp.237-242, 北九州, 2016年5月13日.

2015年度

  1. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.34, no.4, pp. 629-641, April 2015.
  2. Trung Anh Dihh, Shigeru Yamashita, Tsung-Yi Ho:  “A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips,” IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences, Vol. E99-A, No. 2 (2016), pp. 570-5789.
  3. Jason H. Anderson1, Yuko Hara-Azumi2, Shigeru YamashitaEffect of LFSR Seeding, Scrambling and Feedback Polynomial on Stochastic Computing Accuracy To Appear in Proc. ACM/IEEE DATE 2014, March, 2016
  4. Ritsuko Muguruma and Shigeru Yamashita, “Stochastic Number Generation with Few Inputs,” in the Proceedings of 29th International Conference on VLSI Design, pp. 128-133 , Jan. 2016
  5. Abhimanyu Yadav, Trung Anh Dinh, Daiki Kitagawa and Shigeru Yamashita, “ILP-Based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips,” in the Proceedings of 29th International Conference on VLSI Design, pp. 355-360, Jan. 2016.
  6. Shigeru YamashitaPin-Count Reduction Techniques for Logic Integrated Digital Microfluidic Biochips 29th International Conference on VLSI Design, M/D-1.2, Jan. 2016. (招待講演）
  7. T. A. Dinh, S. Yamashita, T.-Y. Ho, and K. Chakrabarty, “A General-PurposeTesting Method for Digital Microfluidic Biochips under Physical Constraints,” in the Proceedings of　IEEE InternationalTest Conference (ITC-2015), pp. 1 - 8, October 2015.
  8. Kouhei Kushida, Teppei Shima and Shigeru YamashitaChanging Specification By Adding Multiple-Control Toffoli Gates forGenerating a Better Initial Reversible Circuitsin Proc. of AQIS 2015, pp. 123-124, Aug. 2015.
  9. Nurul Ain Binti Adnan and Shigeru YamashitaChangingReordering of Multiple-Control Toffoli gates for Better Decomposition in Proc. of AQIS 2015, pp. 127-128, Aug. 2015.
  10. Koutarou Hoshi, Yousef Mohammed Alhamdan Alhamdan, Shigeru Yamashita, Simon Devitt and Kae Nemoto Reduction of Computational Steps for Topological Quantum Computationalby Inserting SWAP gatesin Proc. of AQIS 2015, pp. 131-132, Aug. 2015.
  11. N. A. B. Adnan, S. Yamashita, K. Nemoto, Reduction of Computational Steps for Topological QuantumCircuits Quantum Programming and Circuits Workshop, June 2015.
  12. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Krishnendu Chakrabarty, “Testing of digital microfluidic biochips with arbitrary layouts,” pp. 1-2, in Proc. of 20th IEEE European Test Symposium (ETS), May 2015.
  13. 壷阪 幸輝、山下 茂 Stochastic Computingに用いる定数を近似する回路の合成手法A-01◎2015 年度情報処理学会関西支部　支部大会, A-01, 2015年9月.
  14. 櫛田 耕平、山下 茂 MPMCTゲートの挿入による論理関数を実現する量子回路のコスト削減手法 2015 年度情報処理学会関西支部　支部大会, A-02, 2015年9月.(学生奨励賞受賞）
  15. 春日井 貴通，山下 茂，原 祐子 Partially-Programmable Circuit を 用いた遅延故障の回避手法, ETNET2016 (26) 2015年3月
  16. 松本 涼平，山下 茂，竹内 尚輝 RQFPゲートを用いた超低消費電力AQFP論理回路の設計手法, ETNET2016 (32) 2015年3月
  17. 後藤 敏宏，山下 茂，Approximate Computing を用いた乗算器の実装および検証, ETNET2016 (35) 2015年3月

2014年度

  1. An Energy-Efficient Patchable Accelerator and Its Design Methods Hiroaki YOSHIDA, Masayuki WAKIZAKA, Shigeru YAMASHITA and Masahiro FUJITA IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E97-A, No.12, pp.2507-2517
  2. “Quantitative Evaluations and Efficient Exploration for Optimal Partially-Programmable Circuits Generation,” Takumi Tsuzuki, Yuko Hara-Azumi, Shigeru Yamashita and Yasuhiko Nakashima, Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 199-204, March 2015.
  3. “Efficient Manipulation of Truth Tables on CUDA for Gate-Level Simulation,” Yuri Ardila, Tatsuyuki Kida and Shigeru Yamashita, Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 427-432, March 2014.
  4. “Single-Flux-Quantum Digital Circuit Design Using Clockless Logic Cells with a Jitter Constraint,” Ryohei Matsumoto and Shigeru Yamashita, Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 293-298, March 2015.
  5. “Evaluation of Approximate SAD Circuits with Error Compensation,” Toshihiro Goto, Yasunori Takagi and Shigeru Yamashita, Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 140-145, March 2015.
  6. Graph-Covering-Based Architectural Synthesis for Programmable Digital Microfluidic Biochips Daiki Kitagawa, Dieu Quang Nguyen, Trung Anh Dinh and Shigeru Yamashita Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 344 - 349, March 2015.
  7. “An Efficient Calculation Method for Reliability Analysis of Logic Circuits,” Masatoshi Tsushima, Yuichi Ikeda and Shigeru Yamashita, Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.211－216, March 2015.
  8. Global Transformation-Based Optimization of Threshold Logic Circuits Maiko Kabu, Takayuki Kasugai, Shigeru Yamashita and Chun-Yao Wang Proc. of Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 311-316, March 2015.
  9. Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita and Yasuhiko Nakashima, “Better-than-DMR Techniques for Yield Improvement,” to appear at IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, MA, USA, May 2014.
  10. N. A. B. Adnan, S. Yamashita, S. Devitt, K. Nemoto, 2D Qubit Layout Optimization for Topological Quantum Computation Lecture Notes in Computer Science Volume 8507, 2014, pp 176-188 (Reversible computation 2014, Jul. 2014.)
  11. N. A. B. Adnan, K. Hoshi, S. Yamashita Mapping Patterns with More Than Two Gates for Quantum Cost Reduction 第31回量子情報技術研究会, 2014-11-QIT, pp. 111-112, 2014年11月．
  12. 【招待講演】山下茂, “SPFDによる論理関数の自由度の表現とその回路設計へ の応用,” 第27回回路とシステム軽井沢ワークショップ予稿集， pp.68-73， 2014年8月.
  13. SATを用いたナンバーリンクソルバーの高速化 池田祐一、津島雅俊、Trung Anh Dinh、山下茂 アルゴリズムデザインコンテスト, DAシンポジウム2014, 2014年8月.
  14. 組み合わせ回路におけるソフトエラー発生確率の効率的計算手法 津島雅俊, 山下茂, 2014年度 情報処理学会関西支部 支部大会, 2014年9月.
  15. SeqBDDのメモリ使用効率化手法 池田祐一, 山下茂, 2014年度 情報処理学会関西支部 支部大会, 2014年9月.
  16. 特許公開「データ処理装置、画像処理装置、データ処理方法、及びコンピュー タプログラム」 特開2014－229263 (P2014-229263A) 2014. 12. 8. 公開

2013年度

  1. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho and Yuko Hara-Azumi, “Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips,” IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E96-A, No.12, pp.2668-2679

  2. Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima,

    “Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication,”

    IEICE Transactions on Information and Systems, Vol. E96-D, No. 1 (2013) pp. 1-8.

  3. 崔英鮮, 山下茂, “ビットごとの排他的論理和を利用した画像の新しい類似度指標の提案とその動き検出プロセッサへの適用と評価,” 電子情報通信学会英文論文誌A, Vol. J97-A, No. 03, pp.160-169, Mar. 2014.

  4. Tanvir Ahmed, Jun Yao, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko

    Nakashima, “Selective Check of Data-Path for Effective Fault Tolerance,”

    IEICE Transactions on Information and Systems (Special Section on

    “Reconfigurable Systems”), vol. E96-D, No.8 (2013) pp.1592-1601

  5. N. A. B. Adnan, S. Yamashita, S. Devitt, K. Nemoto, “2D Qubit Layout Optimization for Topological Quantum,” Proc. of RC’2014, To Appear, Jul. 2014.

  6. Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita and Yasuhiko Nakashima, “Better-than-DMR Techniques for Yield Improvement,” to appear at IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, MA, USA, May 2014.

  7. Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita and Yasuhiko Nakashima, “Novel Area-Efficient Technique for Yield Improvement,” Electronic System-Level Design towards Heterogeneous Computing in conjunction with Design, Automation & Test in Europe (DATE), Dresden, Germany, Mar. 2014. (Poster)

  8. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, “A Network-Flow-Based Optimal Sample Preparation Algorithms for Digital Microfluidic Biochips,” To appear in Proc. ACM/IEEE ASP-DAC 2014, pp. 225-230, Jan. 2014. (Best Paper Candidate)

  9. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, “A Logic Integrated Optimal Pin-Count Design for Digital Microfluidic Biochips,” in Proc. ACM/IEEE DATE 2014, pp. 1-6, March, 2014

  10. Atsushi Matsuo, Yasunori Takagi, Hiroki Nakahara, Shigeru Yamashita, “A Variable-Length String Matching Circuit Based On SeqBDDs,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 282 - 287, Oct. 2013

  11. P. Balasubramanian, S. Yamashita, “On the Error Resiliency of Combinational Logic Cells – Implications for Nano-based Digital Design,” Proc. 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, pp. 118-119, Dec. 2013.

  12. S. Yamashita, S. Hiratsuka, S. Devitt, K. Nemoto, “Qubit Arrangement Problems for Topological Quantum Computation,” Proc. of AQIS’13, pp. 181-182, Aug. 2013.

  13. 山下茂, “可逆な素子による論理設計の研究動向（招待講演）,” 応用物理学会 (超伝導分科会 第48回研究会), (独)産業技術総合研究所つくばセンター中央第2, 2-12棟, 第6会議室, 2013年11月22日

  14. 山下茂, “可逆計算に関する研究動向（招待講演）,” 日本学術振興会超伝導エレクトロニクス第146委員会通信・情報処理分科会第9回研究会, 2013年7月22日（月）, 機械振興会館

  15. 早苗駿一, 原祐子, 山下茂, 中島康彦, “Partially-Programmable Circuitの歩留まり向上のためのLUT最適化手法 (優秀発表学生賞),” DAシンポジウム2013, 2B-1, 2013年8月21日

  16. ディン アイン チュン, 山下茂, ツン イ ホー, “Digital Microfluidic Biochip向けの最適な試料生成 (優秀発表学生賞),” 信学技報, vol. 113, no. 320, VLD2013-64, pp. 19-24, 2013年11月27日.

  17. 早苗駿一, 原祐子, 山下茂, 中島康彦, “PPCに基づく高歩留まり回路の発見的設計手法,” 信学技報, vol. 113, no. 320, VLD2013-65, pp. 27-32, 2013年11月27日.

  18. 松尾惇, 山下茂, “二重化よりも面積オーバーヘッドが少ない耐故障化手法,” 信学技報, vol. 113, no. 320, VLD2013-66, pp. 33-37, 2013年11月27日.

  19. ディン アイン チュン, 山下茂, ツン イ ホー, “A Network-Flow-Based Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips,” VLSI設計技術研究会, VLD Excellent Student Award記念講演, 2014/03/04

2012年度

  1. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi, “A Clique-Based Approach to Find Binding and Scheduling Result in Flow-Based Microfluidic Biochips,” in Proc. of ASP-DAC'13, pp.199-204, Jan. 2012
  2. M. Villagra, M. Nakanishi, S. Yamashita, Y. Nakashima, “Quantum walks on the line with phase parameters,” IEICE Transactions on Information and Systems, vol. E95-D, no.3 pp.722-730, Mar. 2012.
  3. Richard Cleve, Kazuo Iwama, Francois Le Gall, Harumichi Nishimura,Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita, “Improved Quantum Algorithms for Reconstructing Strings from Substrings,” Asian Association for Algorithms and Computatio n(AAAC2012), Apr. 2012.
  4. Hiroshi Aoki, Shigeru Yamashita and Sin-ichi Minato, “Sequence Binary Decision Diagrams with Mapping Edges,” IEICE-COMP2012-4, pp.23–28, Apr. 2012.
  5. Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima, “Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication,” TAMC 2012, May. 2012.
  6. S. Yamashita, S. Devitt, K. Nemoto, “Qubit Order Optimization　Problem for Topological Quantum Computation,” TQC2012, May. 2012.
  7. Richard Cleve, Kazuo Iwama, Francois Le Gall, Harumichi, Nishimura,Seiichiro Tani, Junichi Teruyama and Shigeru Yamashita, “Reconstructing Strings from Substrings with Quantum Queries,” in Proc. of (SWAT 2012), pp.388-397, July. 2012.
  8. S. Yamashita, S. Hiratsuka, S. Devitt, K. Nemoto, “Circuit Optimization by Clique Finding for Topological Quantum Computation,” in Proc. of AQIS’12, pp.161-162, Aug. 2012.
  9. 山下茂, 「OHM大学テキスト コンピュータアーキテクチャ（1章、2章、5章担当）」，オーム社，2012年9月
  10. 伊藤 洋平, 青木 洋士, 山下 茂, 「SeqBDDにおける最長共通部分列・部分文字列アルゴリズム」, 平成24年度情報処理学会関西支部大会B-04, 2012年9月.
  11. S. Yamashita, “An Optimization Problem for Topological Quantum Computation,” in Proc. of IEEE ATS'12, pp.61-66, Nov. 2012 (招待講演).
  12. Atsushi Matsuo, Shigeru Yamashita, Hiroaki Yoshida, “Partially-Programmable Circuits with CAMs,” デザインガイア2012, VLD2012-64, pp.31-36, 2012年11月.
  13. Masayuki Wakizaka, Hiroaki Yoshida, Yuko Hara-Azumi and Shigeru Yamashita, “A Redundant Wire Addition Method for Patchable Accelerator,” in Proc. of The 2012 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp.552-555, Dec. 2012.
  14. M. Villagra, M. Nakanishi, S. Yamashita, Y. Nakashima, “Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication,” IEICE Transactions on Information and Systems, Vol. E96-D, no.1, pp.1-8, Jan. 2013.

2011年度

  1. Yuko Hara-Azumi, Hiroyuki Tomiyama, Takuya Azumi, Shigeru Yamashita, Nikil D. Dutt, and Hiroaki Takada, “Soft Error-Aware Scheduling in High-Level Synthesis (in English),” 電子情報通信学会技術研究報告, vol.2011-SLDM-149/vol.2011-EMB-20, no.19, pp.1-6, Mar. 2011.
  2. 青木洋士, 山下茂, 湊真一, “逆順の系列集合を表すSeqBDDの構築,” 電子情報通信学会技術研究報告, COMP, コンピュテーション, vol.111, no.20, pp.17-23, Apr. 2011.
  3. Richard Cleve, Kazuo Iwama, Francois Le Gall, Harumichi　Nishimura,Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita, “Reconstructing　 Strings from Substrings with Quantum Queries,”　Asian Association forAlgorithms and Computation (AAAC2011), 　Apr. 2011.
  4. Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller,“Synthesis of Semi-Classical Quantum Circuits,“Journal of Multiple-Valued Logic and Soft Computing, 2011, pp. 99-114.
  5. Shigeru Yamashita, Masaki Nakanishi, “An Efficient Framework to Utilize Grover Search,“Journal of Nanjing University of Posts and Telecommunications, Vol. 31, No.2, pp. 85-94, Apr. 2011.
  6. Atsushi Matsuo, Shigeru Yamashita , “Changing the Gate Order for Optimal LNN Conversion”, Reversible Computation, July. 2011.
  7. 鶴田 大貴, 安積(原) 祐子, 山下 茂, “リソースの再利用による実装面積を考慮した耐故障化高位合成手法 (in Japanese),” DAシンポジウム 2011 論文集, pp. 15-20, Aug, 2011.
  8. M. Villagra, M. Nakanishi, S. Yamashita, Y. Nakashima, “Quantum Query Complexity of Hamming Distance Estimation,” in Proc. of AQIS’11, pp. 103-104, Aug, 2011.
  9. 浜地亮輔, 山下茂, “SAD演算回路における最適な比較ビット使用箇所およびブロックサイズの検討,” 情報処理学会関西支部支部大会, Sep. 2011
  10. H. Aoki and S. Yamashita and S. Minato “An Efficient Algorithm for Constructing a Sequence Binary Decision Diagram Representing a Set of Reversed Sequences,” IEEE International Conference on Granular Computing 2011, pp. 54-55, Nov, 2011.
  11. S. Yamashita, S. Devitt, K. Nemoto, “Logic level circuit ooptimization for topological quantum computation”, in Proc. of QIT25, pp. 185-188, Nov, 2011.
  12. S. Yamashita, “Logic level circuit optimization for topological quantum computation (Invited Talk),” Dagstuhl Seminar 11502: Design of Reversible and Quantum Circuits, Dec, 2011
  13. Hratch Mangassarian, Hiroaki Yoshida, Andreas Veneris, Shigeru Yamashita, Masahiro Fujita, “On Error Tolerance and Engineering Change with Partially Programmable Circuits,” ASP-DAC'12, pp. 695-700, Feb, 2012.
  14. Yuko Hara-Azumi and Hiroyuki Tomiyama, “Clock-Constrained Simultaneous Allocation and Binding for Multiplexer Optimization in High-Level Synthesis,” Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 251-256, Feb. 2012.
  15. 伊藤洋平, 青木洋士, 山下茂, “SeqBDDにおける最長共通部分列・部分文字列アルゴリズム,” 電子情報通信学会関西支部学生会 第17回学生会研究発表講演会, Mar, 2012.
  16. 平塚進之介, 山下茂, “トポロジカル量子コンピュータにおける量子回路の最適化手法,” 電子情報通信学会関西支部学生会 第17回学生会研究発表講演会, Mar, 2012.
  17. Yuri Ardila, Shigeru Yamashita, “Evaluation of Migration Methods for Island Based Parallel Genetic Algorithm on CUDA,” Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 378-383, Mar, 2012.
  18. Yuko Hara-Azumi, Hiroyuki Tomiyama, Shigeru Yamashita, and Nikil D. Dutt, “High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement,” Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 414-419, Mar, 2012.
  19. Daiki Tsuruta, Masayuki Wakizaka, Yuko Hara-Azumi, and Shigeru Yamashita, “A TMR-based Soft Error Mitigation Technique With Less Area Overhead in High-Level Synthesis”, Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 396-401, Mar, 2012.
  20. Ryosuke Hamaji, Yongson Choi, Yuko Hara-Azumi, and Shigeru Yamashita, “Bit Selective SAD and Its Evaluation,” Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 22-27, Mar, 2012.

2010年度

  1. Yuichi Hirata, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima, “An efficient conversion of quantum circuits to a linear  nearest neighbor architecture,”  Quantum Information and Computation,Vol. 11, No. 1, pp. 142-166, Jan. 2011.
  2. 松尾惇士, 山下茂, “ゲート順序を考慮したLNNアーキテクチャへの変換手法,” 量子情報技術研究会, Nov. 2010.
  3. “Increasing Yield Using Partially-Programmable Circuits,”　ShigeruYamashita, Hiroaki Yoshida, Masahiro Fujita,　Proc. of Conference of Synthesis And System Integration of MixedInformation technologies (SASIMI2010), pp. 237-242 (Best Paper Award), Oct. 2010.
  4. S. Yamashita, I. L. Markov, “Fast equivalence-checking for quantum   circuit,” Quantum Information and Computation, Vol. 10, No. 9&10, pp. 721-734, Sep. 2010.
  5. 山下茂, “量子探索アルゴリズムとその利用（招待論文）",電子情報通信学会会誌, Vol. 93, No. 9, pp. 785-791, Sep. 2010.
  6. “A SAT Solver Based on Quantum and Classical Random Walks,” D. Yokomine, M. Nakanishi, S. Yamashita, and Y. Nakashima,Asian Conference on Quantum Information Science 2010 (AQIS2010), Aug. 2010.
  7. “Asymptotics of Quantum Walks on the Line with Phase Parameters,“M. Villagra, M. Nakanishi, S. Yamashita, and Y. Nakashima,  AsianConference on Quantum Information Science 2010 (AQIS2010), Aug. 2010.
  8. “Synthesis of Semi-Classical Quantum Circuits,” S. Yamashita,S. Minato, D. M. Miller, Proc. of 2nd Workshop on ReversibleComputation, pp. 93-99, Jul. 2010.
  9. “Fast Equivalence-checking for Quantum Circuits,“Shigeru Yamashita, Igor Markov, Proc. of NANOARCH'10, pp. 23 - 28,Jun. 2010.
  10. 柴田章博, 中田尚, 中西正樹, 山下茂, 中島康彦, “量子計算の並列シミュレー ションにおける通信量削減手法”,電子情報通信学会論文誌, Vo. J93-D, No. 3, pp. 253-264, Mar. 2010.