対外発表論文一覧

2012年度

1. Richard Cleve, Kazuo Iwama, Francois Le Gall, Harumichi Nishimura,Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita, “Improved Quantum Algorithms for Reconstructing Strings from Substrings,” Asian Association for Algorithms and Computation (AAAC2011), Apr, 2012.
2. Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima, “Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication,” TAMC 2012, May, 2012.

2011年度

1. Yuko Hara-Azumi, Hiroyuki Tomiyama, Takuya Azumi, Shigeru Yamashita, Nikil D. Dutt, and Hiroaki Takada, “Soft Error-Aware Scheduling in High-Level Synthesis (in English),” 電子情報通信学会技術研究報告, vol.2011-SLDM-149/vol.2011-EMB-20, no.19, pp.1-6, Mar. 2011.
2. 青木洋士, 山下茂, 湊真一, “逆順の系列集合を表すSeqBDDの構築,” 電子情報通信学会技術研究報告, COMP, コンピュテーション, vol.111, no.20, pp.17-23, Apr. 2011.
3. Richard Cleve, Kazuo Iwama, Francois Le Gall, Harumichi　Nishimura,Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita, “Reconstructing　 Strings from Substrings with Quantum Queries,”　Asian Association forAlgorithms and Computation (AAAC2011), 　Apr. 2011.
4. Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller,”Synthesis of Semi-Classical Quantum Circuits,”Journal of Multiple-Valued Logic and Soft Computing, 2011, pp. 99-114.
5. Shigeru Yamashita, Masaki Nakanishi, “An Efficient Framework to Utilize Grover Search,”Journal of Nanjing University of Posts and Telecommunications, Vol. 31, No.2, pp. 85-94, Apr. 2011.
6. Atsushi Matsuo, Shigeru Yamashita , “Changing the Gate Order for Optimal LNN Conversion”, Reversible Computation, July. 2011.
7. 鶴田 大貴, 安積(原) 祐子, 山下 茂, “リソースの再利用による実装面積を考慮した耐故障化高位合成手法 (in Japanese),” DAシンポジウム 2011 論文集, pp. 15-20, Aug, 2011.
8. M. Villagra, M. Nakanishi, S. Yamashita, Y. Nakashima, “Quantum Query Complexity of Hamming Distance Estimation,” in Proc. of AQIS’11, pp. 103-104, Aug, 2011.
9. 浜地亮輔, 山下茂, “SAD演算回路における最適な比較ビット使用箇所およびブロックサイズの検討,” 情報処理学会関西支部支部大会, Sep. 2011
10. H. Aoki and S. Yamashita and S. Minato “An Efficient Algorithm for Constructing a Sequence Binary Decision Diagram Representing a Set of Reversed Sequences,” IEEE International Conference on Granular Computing 2011, pp. 54-55, Nov, 2011.
11. S. Yamashita, S. Devitt, K. Nemoto, “Logic level circuit ooptimization for topological quantum computation”, in Proc. of QIT25, pp. 185-188, Nov, 2011.
12. S. Yamashita, “Logic level circuit optimization for topological quantum computation (Invited Talk),” Dagstuhl Seminar 11502: Design of Reversible and Quantum Circuits, Dec, 2011
13. Hratch Mangassarian, Hiroaki Yoshida, Andreas Veneris, Shigeru Yamashita, Masahiro Fujita, “On Error Tolerance and Engineering Change with Partially Programmable Circuits,” ASP-DAC’12, pp. 695-700, Feb, 2012.
14. Yuko Hara-Azumi and Hiroyuki Tomiyama, “Clock-Constrained Simultaneous Allocation and Binding for Multiplexer Optimization in High-Level Synthesis,” Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 251-256, Feb. 2012.
15. 伊藤洋平, 青木洋士, 山下茂, “SeqBDDにおける最長共通部分列・部分文字列アルゴリズム,” 電子情報通信学会関西支部学生会 第17回学生会研究発表講演会, Mar, 2012.
16. 平塚進之介, 山下茂, “トポロジカル量子コンピュータにおける量子回路の最適化手法,” 電子情報通信学会関西支部学生会 第17回学生会研究発表講演会, Mar, 2012.
17. Yuri Ardila, Shigeru Yamashita, “Evaluation of Migration Methods for Island Based Parallel Genetic Algorithm on CUDA,” Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 378-383, Mar, 2012.
18. Yuko Hara-Azumi, Hiroyuki Tomiyama, Shigeru Yamashita, and Nikil D. Dutt, “High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement,” Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 414-419, Mar, 2012.
19. Daiki Tsuruta, Masayuki Wakizaka, Yuko Hara-Azumi, and Shigeru Yamashita, “A TMR-based Soft Error Mitigation Technique With Less Area Overhead in High-Level Synthesis”, Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 396-401, Mar, 2012.
20. Ryosuke Hamaji, Yongson Choi, Yuko Hara-Azumi, “Bit Selective SAD and Its Evaluation,” Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 22-27, Mar, 2012.

2010年度

1. Yuichi Hirata, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima, “An efficient conversion of quantum circuits to a linear  nearest neighbor architecture,”  Quantum Information and Computation,Vol. 11, No. 1, pp. 142-166, Jan. 2011.
2. 松尾惇士, 山下茂, “ゲート順序を考慮したLNNアーキテクチャへの変換手法,” 量子情報技術研究会, Nov. 2010.
3. “Increasing Yield Using Partially-Programmable Circuits,”　ShigeruYamashita, Hiroaki Yoshida, Masahiro Fujita,　Proc. of Conference of Synthesis And System Integration of MixedInformation technologies (SASIMI2010), pp. 237-242 (Best Paper Award), Oct. 2010.
4. S. Yamashita, I. L. Markov, “Fast equivalence-checking for quantum   circuit,” Quantum Information and Computation, Vol. 10, No. 9&10, pp. 721-734, Sep. 2010.
5. 山下茂, “量子探索アルゴリズムとその利用（招待論文）”,電子情報通信学会会誌, Vol. 93, No. 9, pp. 785-791, Sep. 2010.
6. “A SAT Solver Based on Quantum and Classical Random Walks,” D. Yokomine, M. Nakanishi, S. Yamashita, and Y. Nakashima,Asian Conference on Quantum Information Science 2010 (AQIS2010), Aug. 2010.
7. “Asymptotics of Quantum Walks on the Line with Phase Parameters,”M. Villagra, M. Nakanishi, S. Yamashita, and Y. Nakashima,  AsianConference on Quantum Information Science 2010 (AQIS2010), Aug. 2010.
8. “Synthesis of Semi-Classical Quantum Circuits,” S. Yamashita,S. Minato, D. M. Miller, Proc. of 2nd Workshop on ReversibleComputation, pp. 93-99, Jul. 2010.
9. “Fast Equivalence-checking for Quantum Circuits,”Shigeru Yamashita, Igor Markov, Proc. of NANOARCH’10, pp. 23 – 28,Jun. 2010.
10. 柴田章博, 中田尚, 中西正樹, 山下茂, 中島康彦, “量子計算の並列シミュレー ションにおける通信量削減手法”,電子情報通信学会論文誌, Vo. J93-D, No. 3, pp. 253-264, Mar. 2010.