対外発表論文一覧

2017年度

  1. 山下茂、「電子情報通信学会 100年史」D 情報・システム 第1章 コンピュータシステム,  1.2 計算理論,並列・分散計算処理の節, 電子情報通信学会, 2017
  2. Graph-Covering-Based Architectural Synthesis for Programmable Digital Microfluidic Biochips, Daiki Kitagawa, Dieu Quang Nguyen, Trung Anh Dinh. Shigeru Yamashita, International Journal of Biomedical and Clinical Engineering (IJBCE), Article 3, Volume 6: 2 Issues (2017)
  3. Stochastic Number Generation with the Minimum Inputs. Ritsuko Muguruma, Shigeru Yamashita, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E100.A (2017) No. 8 pp. 1661-1671.
  4. Reduction of Quantum Cost by Making Temporary Changes to the Function, Nurul Ain Binti Adnan, Shigeru Yamashita, Alan Mischenko, IEICE Transactions on Information and Systems, Vol. E100.D (2017) No. 7 pp. 1393-1402
  5. A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers, Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, Volume E100-A No.7, pp.1496-1499.
  6. 山元 貴普, 谷口 一徹, 冨山 宏之, 山下 茂, 原 祐子,  “改良型配列型近似乗算器の設計と解析,” 回路とシステムワークショップ, 2017年5月.
  7. Systematic Design of Approximate Array Multipliers with Different Accuracy, Takahiro Yamamoto, Hiroyuki Tomiyama, Ittetsu Taniguchi, Shigeru Yamashita, and Yuko ara-Azumi, In International Workshop on Highly Efficient Neural Networks Design, 2017
  8. An Ancilla Reduction Technique for Quantum Circuits Converted from NAND-based Circuits, Soma Esaki, Masato Onoda and Shigeru Yamashita, in Proc. of AQIS 2017, pp. 289-290, Sep. 2017
  9. Synthesis of Physical-Limitation-Aware Optimal Quantum Circuits in 2-D Architecture, Jingwen Ding and Shigeru Yamashia, in Proc. of AQIS 2017, pp. 298-299, Sep. 2017.
  10. Quantum Circuit Design by Using ESOP Minimization,  Masato Onoda and Shigeru Yamashita, in Proc. of AQIS 2017, pp. 423-424, Sep. 2017.
  11. Locating Loops for TCSC Considering Bridge Transformation, Kentaro Haneda and Shigeru Yamashita, in Proc. of AQIS 2017, pp .425-426, Sep. 2017

 2016年度

  1. Ambainis, K. Iwama, M. Nakanishi, H. Nishimura, R. Raymond, S. Tani, S. Yamashita, “Quantum Query Complexity of Almost All Functions with Fixed On-Set Size,” Computational Complexity,Volume 25, Issue 4, pp 723–735, December 2016, Springer International Publishing.
  2.  Masato Onoda, Kouhei Kushida and Shigeru Yamashita, “Optimization of Quantum Circuits with Multiple Outputs,” in Proc. of AQIS 2016, pp. 188-189, Aug. 2016.
  3. Kotaro Hoshi and Shigeru Yamashita, “Parallelization of Braiding Operations for Topological Quantum Computation,” in Proc. of AQIS 2016, pp. 190 -191, Aug. 2016.
  4. Kentaro Haneda, Shigeru Yamashita, Simon Devitt and Kae Nemoto “Reducing Loops for Topological Cluster State Quantum Computation,” in Proc. of AQIS 2016, pp.208 -209, Aug. 2016.
  5. Nurul Ain Binti Adnan, Kouhei Kushida and Shigeru Yamashita
    Reduction of Quantum Cost by Changing the Functionality, in Proc. of AQIS 2016, pp. 212-213, Aug. 2016.
  6. Ain Binti Adnan, Kouhei Kushida and Shigeru Yamashita,”A Pre-Optimization Technique to Generate Initial Reversible Circuits with Low Quantum Cost,”  Proc. of 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2298-3001, May 2016.
  7. Kodai Abe, Shigeru Yamshita, “A Decision Diagram to Analyze Probabilistic Behavior of Circuits, ” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), R2-6, Oct. 2016.
  8. Balasubramanian and S. Yamashita, “Area/Latency Optimized Early Output Asynchronous Full Adders and RelativeTimed Ripple Carry Adders,” SpringerPlus, 5(1), 1-26, 2016.
  9. Yamamoto, I. Taniguchi, H. Tomiyama, S. Yamashita and Y. Hara-Azumi, “A systematic methodology for design and analysis of approximate array multipliers,” 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, 2016, pp. 352-354.
  10. 渡邉 朗弘,山下 茂, “Stochastic Computingにおける相関の許容によるSNGの削減,”  ETNET2017 (19),  2017年3月9日.
  11. 壷阪 幸輝,山下 茂, “Stochastic Computingにおけるマルチプレクサの制御入力として複雑な式を用いる回路設計,” ETNET2017 (20) 2017年3月9日.
  12. 北川 大樹,山下 茂, “試料生成における汚染問題を考慮したDMFB合成手法,” ETNET2017 (21) 2017年3月9日.
  13. 六車利都子, 山下茂,  “最小の入力数でStochastic Numberを生成する回路設計手法, ” 電子情報通信学会技術研究報告 116(330), 1-6, 2016-11-28.
  14. ⼩野⽥ 将⼈、⼭下 茂、櫛⽥ 耕平, “複数出⼒を考慮した量⼦回路設計⼿法,”  2016 年度情報処理学会関西支部支部大会,  G-20, 2016年9月26日. 学生優秀発表賞
  15. ⽻⽥ 健太郎、⼭下 茂、Simon Devitt、根本 ⾹絵, “クラスタ状態TQC回路のループ削減⼿法,” 2016 年度情報処理学会関西支部 支部大会,  G-20, 2016年9月26日. 支部大会奨励賞受賞
  16.  山元 貴普, 谷口 一徹, 冨山 宏之, 山下 茂, 原 祐子, “配列型近似乗算器の設計と解析,” 回路とシステムワークショップ, pp.237-242, 北九州, 2016年5月13日.

2015年度

  1. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
    vol.34, no.4, pp. 629-641, April 2015.
  2. Trung Anh Dihh, Shigeru Yamashita, Tsung-Yi Ho:  “A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips,” IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences, Vol. E99-A, No. 2 (2016),
    pp. 570-5789.
  3. Jason H. Anderson1, Yuko Hara-Azumi2, Shigeru YamashitaEffect of LFSR
    Seeding, Scrambling and Feedback Polynomial on Stochastic Computing Accuracy To Appear in Proc. ACM/IEEE DATE 2014, March, 2016
  4. Ritsuko Muguruma and Shigeru Yamashita, “Stochastic Number Generation with Few Inputs,” in the Proceedings of 29th International Conference on VLSI Design, pp. 128-133 , Jan. 2016
  5. Abhimanyu Yadav, Trung Anh Dinh, Daiki Kitagawa and Shigeru Yamashita, “ILP-Based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips,” in the Proceedings of 29th International
    Conference on VLSI Design, pp. 355-360, Jan. 2016.
  6. Shigeru YamashitaPin-Count Reduction Techniques for Logic Integrated
    Digital Microfluidic Biochips 29th International Conference on VLSI Design, M/D-1.2, Jan. 2016. (招待講演)
  7. T. A. Dinh, S. Yamashita, T.-Y. Ho, and K. Chakrabarty, “A General-PurposeTesting Method for Digital Microfluidic Biochips under Physical Constraints,” in the Proceedings of IEEE InternationalTest Conference (ITC-2015), pp. 1 – 8, October 2015.
  8. Kouhei Kushida, Teppei Shima and Shigeru YamashitaChanging Specification By Adding Multiple-Control Toffoli Gates forGenerating a Better Initial Reversible Circuitsin Proc. of AQIS 2015, pp. 123-124, Aug. 2015.
  9. Nurul Ain Binti Adnan and Shigeru YamashitaChangingReordering of Multiple-Control Toffoli gates for Better Decomposition in Proc. of AQIS 2015, pp. 127-128, Aug. 2015.
  10. Koutarou Hoshi, Yousef Mohammed Alhamdan Alhamdan, Shigeru Yamashita,
    Simon Devitt and Kae Nemoto Reduction of Computational Steps for Topological Quantum Computationalby Inserting SWAP gatesin Proc. of AQIS 2015, pp. 131-132, Aug. 2015.
  11. N. A. B. Adnan, S. Yamashita, K. Nemoto, Reduction of Computational Steps for Topological QuantumCircuits Quantum Programming and Circuits Workshop, June 2015.
  12. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Krishnendu Chakrabarty, “Testing of digital microfluidic biochips with arbitrary layouts,” pp. 1-2, in Proc. of 20th IEEE European Test Symposium (ETS), May 2015.
  13. 壷阪 幸輝、山下 茂 Stochastic Computingに用いる定数を近似する回路の合成手法A-01◎2015 年度情報処理学会関西支部 支部大会, A-01, 2015年9月.
  14. 櫛田 耕平、山下 茂MPMCTゲートの挿入による論理関数を実現する量子回路の
    コスト削減手法 2015 年度情報処理学会関西支部 支部大会, A-02, 2015年9月.(学生奨励賞受賞)
  15. 春日井 貴通,山下 茂,原 祐子 Partially-Programmable Circuit を 用いた遅延故障の回避手法, ETNET2016 (26) 2015年3月
  16. 松本 涼平,山下 茂,竹内 尚輝 RQFPゲートを用いた超低消費電力AQFP論理回路の設計手法, ETNET2016 (32) 2015年3月
  17. 後藤 敏宏,山下 茂,竹内Approximate Computing を用いた乗算器の実装および検証, ETNET2016 (35) 2015年3月

2014年度

  1. An Energy-Efficient Patchable Accelerator and Its Design Methods
    Hiroaki YOSHIDA, Masayuki WAKIZAKA, Shigeru YAMASHITA and Masahiro
    FUJITA IEICE TRANSACTIONS on Fundamentals of Electronics,
    Communications and Computer Sciences Vol.E97-A, No.12, pp.2507-2517
  2. “Quantitative Evaluations and Efficient Exploration for Optimal
    Partially-Programmable Circuits Generation,”
    Takumi Tsuzuki, Yuko Hara-Azumi, Shigeru Yamashita and Yasuhiko Nakashima,
    Proc. Workshop on Synthesis And System Integration of Mixed
    Information Technologies (SASIMI), pp. 199-204, March 2015.
  3. “Efficient Manipulation of Truth Tables on CUDA for Gate-Level Simulation,”
    Yuri Ardila, Tatsuyuki Kida and Shigeru Yamashita,
    Proc. Workshop on Synthesis And System Integration of Mixed
    Information Technologies (SASIMI), pp. 427-432, March 2014.
  4. “Single-Flux-Quantum Digital Circuit Design Using Clockless Logic Cells
    with a Jitter Constraint,”
    Ryohei Matsumoto and Shigeru Yamashita,
    Proc. Workshop on Synthesis And System Integration of Mixed
    Information Technologies (SASIMI), pp. 293-298, March 2015.
  5. “Evaluation of Approximate SAD Circuits with Error Compensation,”
    Toshihiro Goto, Yasunori Takagi and Shigeru Yamashita,
    Proc. Workshop on Synthesis And System Integration of Mixed
    Information Technologies (SASIMI), pp. 140-145, March 2015.
  6. Graph-Covering-Based Architectural Synthesis for Programmable Digital Microfluidic Biochips
    Daiki Kitagawa, Dieu Quang Nguyen, Trung Anh Dinh and Shigeru Yamashita
    Proc. Workshop on Synthesis And System Integration of Mixed
    Information Technologies (SASIMI), pp. 344 – 349, March 2015.
  7. “An Efficient Calculation Method for Reliability Analysis of Logic Circuits,”
    Masatoshi Tsushima, Yuichi Ikeda and Shigeru Yamashita,
    Proc. Workshop on Synthesis And System Integration of Mixed
    Information Technologies (SASIMI), pp.211-216, March 2015.
  8. Global Transformation-Based Optimization of Threshold Logic Circuits
    Maiko Kabu, Takayuki Kasugai, Shigeru Yamashita and Chun-Yao Wang
    Proc. of Proc. Workshop on Synthesis And System Integration of Mixed
    Information Technologies (SASIMI), pp. 311-316, March 2015.
  9. Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita and Yasuhiko
    Nakashima, “Better-than-DMR Techniques for Yield Improvement,” to
    appear at IEEE International Symposium on Field-Programmable
    Custom Computing Machines (FCCM), Boston, MA, USA, May 2014.
  10. N. A. B. Adnan, S. Yamashita, S. Devitt, K. Nemoto,
    2D Qubit Layout Optimization for Topological Quantum Computation
    Lecture Notes in Computer Science Volume 8507, 2014, pp 176-188
    (Reversible computation 2014, Jul. 2014.)
  11. N. A. B. Adnan, K. Hoshi, S. Yamashita
    Mapping Patterns with More Than Two Gates for Quantum Cost Reduction
    第31回量子情報技術研究会, 2014-11-QIT, pp. 111-112, 2014年11月.
  12. 【招待講演】山下茂, “SPFDによる論理関数の自由度の表現とその回路設計へ
    の応用,” 第27回回路とシステム軽井沢ワークショップ予稿集, pp.68-73,
    2014年8月.
  13. SATを用いたナンバーリンクソルバーの高速化
    池田祐一、津島雅俊、Trung Anh Dinh、山下茂
    アルゴリズムデザインコンテスト, DAシンポジウム2014, 2014年8月.
  14. 組み合わせ回路におけるソフトエラー発生確率の効率的計算手法
    津島雅俊, 山下茂, 2014年度 情報処理学会関西支部 支部大会, 2014年9月.
  15. SeqBDDのメモリ使用効率化手法
    池田祐一, 山下茂, 2014年度 情報処理学会関西支部 支部大会, 2014年9月.
  16. 特許公開「データ処理装置、画像処理装置、データ処理方法、及びコンピュー
    タプログラム」 特開2014-229263 (P2014-229263A) 2014. 12. 8. 公開

2013年度

  1. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho and Yuko Hara-Azumi, “Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips,” IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E96-A, No.12, pp.2668-2679
  2. Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima,

    “Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication,”

    IEICE Transactions on Information and Systems, Vol. E96-D, No. 1 (2013) pp. 1-8.

  3. 崔英鮮, 山下茂, “ビットごとの排他的論理和を利用した画像の新しい類似度指標の提案とその動き検出プロセッサへの適用と評価,” 電子情報通信学会英文論文誌A, Vol. J97-A, No. 03, pp.160-169, Mar. 2014.
  4. Tanvir Ahmed, Jun Yao, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko

    Nakashima, “Selective Check of Data-Path for Effective Fault Tolerance,”

    IEICE Transactions on Information and Systems (Special Section on

    “Reconfigurable Systems”), vol. E96-D, No.8 (2013) pp.1592-1601

  5. N. A. B. Adnan, S. Yamashita, S. Devitt, K. Nemoto, “2D Qubit Layout Optimization for Topological Quantum,” Proc. of RC’2014, To Appear, Jul. 2014.
  6. Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita and Yasuhiko Nakashima, “Better-than-DMR Techniques for Yield Improvement,” to appear at IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, MA, USA, May 2014.
  7. Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita and Yasuhiko Nakashima, “Novel Area-Efficient Technique for Yield Improvement,” Electronic System-Level Design towards Heterogeneous Computing in conjunction with Design, Automation & Test in Europe (DATE), Dresden, Germany, Mar. 2014. (Poster)
  8. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, “A Network-Flow-Based Optimal Sample Preparation Algorithms for Digital Microfluidic Biochips,” To appear in Proc. ACM/IEEE ASP-DAC 2014, pp. 225-230, Jan. 2014. (Best Paper Candidate)
  9. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, “A Logic Integrated Optimal Pin-Count Design for Digital Microfluidic Biochips,” in Proc. ACM/IEEE DATE 2014, pp. 1-6, March, 2014
  10. Atsushi Matsuo, Yasunori Takagi, Hiroki Nakahara, Shigeru Yamashita, “A Variable-Length String Matching Circuit Based On SeqBDDs,” Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 282 – 287, Oct. 2013
  11. P. Balasubramanian, S. Yamashita, “On the Error Resiliency of Combinational Logic Cells – Implications for Nano-based Digital Design,” Proc. 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, pp. 118-119, Dec. 2013.
  12. S. Yamashita, S. Hiratsuka, S. Devitt, K. Nemoto, “Qubit Arrangement Problems for Topological Quantum Computation,” Proc. of AQIS’13, pp. 181-182, Aug. 2013.
  13. 山下茂, “可逆な素子による論理設計の研究動向(招待講演),” 応用物理学会 (超伝導分科会 第48回研究会), (独)産業技術総合研究所つくばセンター中央第2, 2-12棟, 第6会議室, 2013年11月22日
  14. 山下茂, “可逆計算に関する研究動向(招待講演),” 日本学術振興会超伝導エレクトロニクス第146委員会通信・情報処理分科会第9回研究会, 2013年7月22日(月), 機械振興会館
  15. 早苗駿一, 原祐子, 山下茂, 中島康彦, “Partially-Programmable Circuitの歩留まり向上のためのLUT最適化手法 (優秀発表学生賞),” DAシンポジウム2013, 2B-1, 2013年8月21日
  16. ディン アイン チュン, 山下茂, ツン イ ホー, “Digital Microfluidic Biochip向けの最適な試料生成 (優秀発表学生賞),” 信学技報, vol. 113, no. 320, VLD2013-64, pp. 19-24, 2013年11月27日.
  17. 早苗駿一, 原祐子, 山下茂, 中島康彦, “PPCに基づく高歩留まり回路の発見的設計手法,” 信学技報, vol. 113, no. 320, VLD2013-65, pp. 27-32, 2013年11月27日.
  18. 松尾惇, 山下茂, “二重化よりも面積オーバーヘッドが少ない耐故障化手法,” 信学技報, vol. 113, no. 320, VLD2013-66, pp. 33-37, 2013年11月27日.
  19. ディン アイン チュン, 山下茂, ツン イ ホー, “A Network-Flow-Based Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips,” VLSI設計技術研究会, VLD Excellent Student Award記念講演, 2014/03/04

2012年度

  1. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi, “A Clique-Based Approach to Find Binding and Scheduling Result in Flow-Based Microfluidic Biochips,” in Proc. of ASP-DAC’13, pp.199-204, Jan. 2012
  2. M. Villagra, M. Nakanishi, S. Yamashita, Y. Nakashima, “Quantum walks on the line with phase parameters,” IEICE Transactions on Information and Systems, vol. E95-D, no.3 pp.722-730, Mar. 2012.
  3. Richard Cleve, Kazuo Iwama, Francois Le Gall, Harumichi Nishimura,Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita, “Improved Quantum Algorithms for Reconstructing Strings from Substrings,” Asian Association for Algorithms and Computatio n(AAAC2012), Apr. 2012.
  4. Hiroshi Aoki, Shigeru Yamashita and Sin-ichi Minato, “Sequence Binary Decision Diagrams with Mapping Edges,” IEICE-COMP2012-4, pp.23–28, Apr. 2012.
  5. Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima, “Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication,” TAMC 2012, May. 2012.
  6. S. Yamashita, S. Devitt, K. Nemoto, “Qubit Order Optimization Problem for Topological Quantum Computation,” TQC2012, May. 2012.
  7. Richard Cleve, Kazuo Iwama, Francois Le Gall, Harumichi, Nishimura,Seiichiro Tani, Junichi Teruyama and Shigeru Yamashita, “Reconstructing Strings from Substrings with Quantum Queries,” in Proc. of (SWAT 2012), pp.388-397, July. 2012.
  8. S. Yamashita, S. Hiratsuka, S. Devitt, K. Nemoto, “Circuit Optimization by Clique Finding for Topological Quantum Computation,” in Proc. of AQIS’12, pp.161-162, Aug. 2012.
  9. 山下茂, 「OHM大学テキスト コンピュータアーキテクチャ(1章、2章、5章担当)」,オーム社,2012年9月
  10. 伊藤 洋平, 青木 洋士, 山下 茂, 「SeqBDDにおける最長共通部分列・部分文字列アルゴリズム」, 平成24年度情報処理学会関西支部大会B-04, 2012年9月.
  11. S. Yamashita, “An Optimization Problem for Topological Quantum Computation,” in Proc. of IEEE ATS’12, pp.61-66, Nov. 2012 (招待講演).
  12. Atsushi Matsuo, Shigeru Yamashita, Hiroaki Yoshida, “Partially-Programmable Circuits with CAMs,” デザインガイア2012, VLD2012-64, pp.31-36, 2012年11月.
  13. Masayuki Wakizaka, Hiroaki Yoshida, Yuko Hara-Azumi and Shigeru Yamashita, “A Redundant Wire Addition Method for Patchable Accelerator,” in Proc. of The 2012 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp.552-555, Dec. 2012.
  14. M. Villagra, M. Nakanishi, S. Yamashita, Y. Nakashima, “Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication,” IEICE Transactions on Information and Systems, Vol. E96-D, no.1, pp.1-8, Jan. 2013.

2011年度

  1. Yuko Hara-Azumi, Hiroyuki Tomiyama, Takuya Azumi, Shigeru Yamashita, Nikil D. Dutt, and Hiroaki Takada, “Soft Error-Aware Scheduling in High-Level Synthesis (in English),” 電子情報通信学会技術研究報告, vol.2011-SLDM-149/vol.2011-EMB-20, no.19, pp.1-6, Mar. 2011.
  2. 青木洋士, 山下茂, 湊真一, “逆順の系列集合を表すSeqBDDの構築,” 電子情報通信学会技術研究報告, COMP, コンピュテーション, vol.111, no.20, pp.17-23, Apr. 2011.
  3. Richard Cleve, Kazuo Iwama, Francois Le Gall, Harumichi Nishimura,Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita, “Reconstructing  Strings from Substrings with Quantum Queries,” Asian Association forAlgorithms and Computation (AAAC2011),  Apr. 2011.
  4. Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller,”Synthesis of Semi-Classical Quantum Circuits,”Journal of Multiple-Valued Logic and Soft Computing, 2011, pp. 99-114.
  5. Shigeru Yamashita, Masaki Nakanishi, “An Efficient Framework to Utilize Grover Search,”Journal of Nanjing University of Posts and Telecommunications, Vol. 31, No.2, pp. 85-94, Apr. 2011.
  6. Atsushi Matsuo, Shigeru Yamashita , “Changing the Gate Order for Optimal LNN Conversion”, Reversible Computation, July. 2011.
  7. 鶴田 大貴, 安積(原) 祐子, 山下 茂, “リソースの再利用による実装面積を考慮した耐故障化高位合成手法 (in Japanese),” DAシンポジウム 2011 論文集, pp. 15-20, Aug, 2011.
  8. M. Villagra, M. Nakanishi, S. Yamashita, Y. Nakashima, “Quantum Query Complexity of Hamming Distance Estimation,” in Proc. of AQIS’11, pp. 103-104, Aug, 2011.
  9. 浜地亮輔, 山下茂, “SAD演算回路における最適な比較ビット使用箇所およびブロックサイズの検討,” 情報処理学会関西支部支部大会, Sep. 2011
  10. H. Aoki and S. Yamashita and S. Minato “An Efficient Algorithm for Constructing a Sequence Binary Decision Diagram Representing a Set of Reversed Sequences,” IEEE International Conference on Granular Computing 2011, pp. 54-55, Nov, 2011.
  11. S. Yamashita, S. Devitt, K. Nemoto, “Logic level circuit ooptimization for topological quantum computation”, in Proc. of QIT25, pp. 185-188, Nov, 2011.
  12. S. Yamashita, “Logic level circuit optimization for topological quantum computation (Invited Talk),” Dagstuhl Seminar 11502: Design of Reversible and Quantum Circuits, Dec, 2011
  13. Hratch Mangassarian, Hiroaki Yoshida, Andreas Veneris, Shigeru Yamashita, Masahiro Fujita, “On Error Tolerance and Engineering Change with Partially Programmable Circuits,” ASP-DAC’12, pp. 695-700, Feb, 2012.
  14. Yuko Hara-Azumi and Hiroyuki Tomiyama, “Clock-Constrained Simultaneous Allocation and Binding for Multiplexer Optimization in High-Level Synthesis,” Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 251-256, Feb. 2012.
  15. 伊藤洋平, 青木洋士, 山下茂, “SeqBDDにおける最長共通部分列・部分文字列アルゴリズム,” 電子情報通信学会関西支部学生会 第17回学生会研究発表講演会, Mar, 2012.
  16. 平塚進之介, 山下茂, “トポロジカル量子コンピュータにおける量子回路の最適化手法,” 電子情報通信学会関西支部学生会 第17回学生会研究発表講演会, Mar, 2012.
  17. Yuri Ardila, Shigeru Yamashita, “Evaluation of Migration Methods for Island Based Parallel Genetic Algorithm on CUDA,” Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 378-383, Mar, 2012.
  18. Yuko Hara-Azumi, Hiroyuki Tomiyama, Shigeru Yamashita, and Nikil D. Dutt, “High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement,” Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 414-419, Mar, 2012.
  19. Daiki Tsuruta, Masayuki Wakizaka, Yuko Hara-Azumi, and Shigeru Yamashita, “A TMR-based Soft Error Mitigation Technique With Less Area Overhead in High-Level Synthesis”, Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 396-401, Mar, 2012.
  20. Ryosuke Hamaji, Yongson Choi, Yuko Hara-Azumi, and Shigeru Yamashita, “Bit Selective SAD and Its Evaluation,” Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp. 22-27, Mar, 2012.

2010年

  1. Yuichi Hirata, Masaki Nakanishi, Shigeru Yamashita and Yasuhiko Nakashima, “An efficient conversion of quantum circuits to a linear  nearest neighbor architecture,”  Quantum Information and Computation,Vol. 11, No. 1, pp. 142-166, Jan. 2011.
  2. 松尾惇士, 山下茂, “ゲート順序を考慮したLNNアーキテクチャへの変換手法,” 量子情報技術研究会, Nov. 2010.
  3. “Increasing Yield Using Partially-Programmable Circuits,” ShigeruYamashita, Hiroaki Yoshida, Masahiro Fujita, Proc. of Conference of Synthesis And System Integration of MixedInformation technologies (SASIMI2010), pp. 237-242 (Best Paper Award), Oct. 2010.
  4. S. Yamashita, I. L. Markov, “Fast equivalence-checking for quantum   circuit,” Quantum Information and Computation, Vol. 10, No. 9&10, pp. 721-734, Sep. 2010.
  5. 山下茂, “量子探索アルゴリズムとその利用(招待論文)”,電子情報通信学会会誌, Vol. 93, No. 9, pp. 785-791, Sep. 2010.
  6. “A SAT Solver Based on Quantum and Classical Random Walks,” D. Yokomine, M. Nakanishi, S. Yamashita, and Y. Nakashima,Asian Conference on Quantum Information Science 2010 (AQIS2010), Aug. 2010.
  7. “Asymptotics of Quantum Walks on the Line with Phase Parameters,”M. Villagra, M. Nakanishi, S. Yamashita, and Y. Nakashima,  AsianConference on Quantum Information Science 2010 (AQIS2010), Aug. 2010.
  8. “Synthesis of Semi-Classical Quantum Circuits,” S. Yamashita,S. Minato, D. M. Miller, Proc. of 2nd Workshop on ReversibleComputation, pp. 93-99, Jul. 2010.
  9. “Fast Equivalence-checking for Quantum Circuits,”Shigeru Yamashita, Igor Markov, Proc. of NANOARCH’10, pp. 23 – 28,Jun. 2010.
  10. 柴田章博, 中田尚, 中西正樹, 山下茂, 中島康彦, “量子計算の並列シミュレー ションにおける通信量削減手法”,電子情報通信学会論文誌, Vo. J93-D, No. 3, pp. 253-264, Mar. 2010.